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gerrit.cesnet.cz / github / trini / u-boot / 0499218dbcc30532bcc1b7b2ee44b8876675bced / . / arch / arm / cpu / armv7 / omap-common / vc.c
blob: e6e5f7893c2c0a1c2b5eb3f1f29a77a3bc8de7a9 [file] [log] [blame]
Nishanth Menona78274b2012-03-01 14:17:37 +0000[diff] [blame]1/*
2 * Voltage Controller implementation for OMAP
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 * Nishanth Menon
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <common.h>
18#include <asm/omap_common.h>
19#include <asm/arch/sys_proto.h>
20
21/*
22 * Define Master code if there are multiple masters on the I2C_SR bus.
23 * Normally not required
24 */
25#ifndef CONFIG_OMAP_VC_I2C_HS_MCODE
26#define CONFIG_OMAP_VC_I2C_HS_MCODE 0x0
27#endif
28
29/* Register defines and masks for VC IP Block */
30/* PRM_VC_CFG_I2C_MODE */
31#define PRM_VC_CFG_I2C_MODE_DFILTEREN_BIT (0x1 << 6)
32#define PRM_VC_CFG_I2C_MODE_SRMODEEN_BIT (0x1 << 4)
33#define PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT (0x1 << 3)
34#define PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT 0x0
35#define PRM_VC_CFG_I2C_MODE_HSMCODE_MASK 0x3
36
37/* PRM_VC_CFG_I2C_CLK */
38#define PRM_VC_CFG_I2C_CLK_HSCLL_SHIFT 24
39#define PRM_VC_CFG_I2C_CLK_HSCLL_MASK 0xFF
40#define PRM_VC_CFG_I2C_CLK_HSCLH_SHIFT 16
41#define PRM_VC_CFG_I2C_CLK_HSCLH_MASK 0xFF
42#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT 0
43#define PRM_VC_CFG_I2C_CLK_SCLH_MASK 0xFF
44#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT 8
45#define PRM_VC_CFG_I2C_CLK_SCLL_MASK (0xFF << 8)
46
47/* PRM_VC_VAL_BYPASS */
48#define PRM_VC_VAL_BYPASS_VALID_BIT (0x1 << 24)
49#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0
50#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F
51#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8
52#define PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF
53#define PRM_VC_VAL_BYPASS_DATA_SHIFT 16
54#define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF
55
56/**
57 * omap_vc_init() - Initialization for Voltage controller
58 * @speed_khz: I2C buspeed in KHz
59 */
60void omap_vc_init(u16 speed_khz)
61{
62 u32 val;
63 u32 sys_clk_khz, cycles_hi, cycles_low;
64
65 sys_clk_khz = get_sys_clk_freq() / 1000;
66
67 if (speed_khz > 400) {
68 puts("higher speed requested - throttle to 400Khz\n");
69 speed_khz = 400;
70 }
71
72 /*
73 * Setup the dedicated I2C controller for Voltage Control
74 * I2C clk - high period 40% low period 60%
75 */
76 speed_khz /= 10;
77 cycles_hi = sys_clk_khz * 4 / speed_khz;
78 cycles_low = sys_clk_khz * 6 / speed_khz;
79 /* values to be set in register - less by 5 & 7 respectively */
80 cycles_hi -= 5;
81 cycles_low -= 7;
82 val = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
83 (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
SRICHARAN R01b753f2013-02-04 04:22:00 +0000[diff] [blame]84 writel(val, (*prcm)->prm_vc_cfg_i2c_clk);
Nishanth Menona78274b2012-03-01 14:17:37 +0000[diff] [blame]85
86 val = CONFIG_OMAP_VC_I2C_HS_MCODE <<
87 PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT;
88 /* No HS mode for now */
89 val &= ~PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT;
SRICHARAN R01b753f2013-02-04 04:22:00 +0000[diff] [blame]90 writel(val, (*prcm)->prm_vc_cfg_i2c_mode);
Nishanth Menona78274b2012-03-01 14:17:37 +0000[diff] [blame]91}
92
93/**
94 * omap_vc_bypass_send_value() - Send a data using VC Bypass command
95 * @sa: 7 bit I2C slave address of the PMIC
96 * @reg_addr: I2C register address(8 bit) address in PMIC
97 * @reg_data: what 8 bit data to write
98 */
99int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data)
100{
101 /*
102 * Unfortunately we need to loop here instead of a defined time
103 * use arbitary large value
104 */
105 u32 timeout = 0xFFFF;
106 u32 reg_val;
107
108 sa &= PRM_VC_VAL_BYPASS_SLAVEADDR_MASK;
109 reg_addr &= PRM_VC_VAL_BYPASS_REGADDR_MASK;
110 reg_data &= PRM_VC_VAL_BYPASS_DATA_MASK;
111
112 /* program VC to send data */
113 reg_val = sa << PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT |
114 reg_addr << PRM_VC_VAL_BYPASS_REGADDR_SHIFT |
115 reg_data << PRM_VC_VAL_BYPASS_DATA_SHIFT;
SRICHARAN R01b753f2013-02-04 04:22:00 +0000[diff] [blame]116 writel(reg_val, (*prcm)->prm_vc_val_bypass);
Nishanth Menona78274b2012-03-01 14:17:37 +0000[diff] [blame]117
118 /* Signal VC to send data */
SRICHARAN R01b753f2013-02-04 04:22:00 +0000[diff] [blame]119 writel(reg_val | PRM_VC_VAL_BYPASS_VALID_BIT,
120 (*prcm)->prm_vc_val_bypass);
Nishanth Menona78274b2012-03-01 14:17:37 +0000[diff] [blame]121
122 /* Wait on VC to complete transmission */
123 do {
SRICHARAN R01b753f2013-02-04 04:22:00 +0000[diff] [blame]124 reg_val = readl((*prcm)->prm_vc_val_bypass) &
Nishanth Menona78274b2012-03-01 14:17:37 +0000[diff] [blame]125 PRM_VC_VAL_BYPASS_VALID_BIT;
126 if (!reg_val)
127 break;
128
129 sdelay(100);
130 } while (--timeout);
131
132 /* Optional: cleanup PRM_IRQSTATUS_Ax */
133 /* In case we can do something about it in future.. */
134 if (!timeout)
135 return -1;
136
137 /* All good.. */
138 return 0;
139}