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Larry Johnsonc591dff2007-12-27 11:28:51 -05001/*
Lawrence R. Johnson0ddd9692008-01-03 15:02:02 -05002 * (C) Copyright 2007-2008
Larry Johnsonc591dff2007-12-27 11:28:51 -05003 * Larry Johnson, lrj@acm.org
4 *
Larry Johnson6433fa22008-03-17 11:10:35 -05005 * (C) Copyright 2006-2007
Larry Johnsonc591dff2007-12-27 11:28:51 -05006 * Stefan Roese, DENX Software Engineering, sr@denx.de.
7 *
8 * (C) Copyright 2006
9 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
Larry Johnson6433fa22008-03-17 11:10:35 -050010 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
Larry Johnsonc591dff2007-12-27 11:28:51 -050011 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
Larry Johnsonc591dff2007-12-27 11:28:51 -050029#include <i2c.h>
30#include <ppc440.h>
Larry Johnson3259eea2008-01-17 08:50:09 -050031#include <asm/gpio.h>
32#include <asm/processor.h>
33#include <asm/io.h>
34#include <asm/bitops.h>
Larry Johnsonc591dff2007-12-27 11:28:51 -050035
36DECLARE_GLOBAL_DATA_PTR;
37
Larry Johnson3259eea2008-01-17 08:50:09 -050038extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
Larry Johnsonc591dff2007-12-27 11:28:51 -050039
40ulong flash_get_size(ulong base, int banknum);
41
Larry Johnson6433fa22008-03-17 11:10:35 -050042#if defined(CONFIG_KORAT_PERMANENT)
43void korat_buzzer(int const on)
44{
45 if (on) {
46 out_8((u8 *) CFG_CPLD_BASE + 0x05,
47 in_8((u8 *) CFG_CPLD_BASE + 0x05) | 0x80);
48 } else {
49 out_8((u8 *) CFG_CPLD_BASE + 0x05,
50 in_8((u8 *) CFG_CPLD_BASE + 0x05) & ~0x80);
51 }
52}
53#endif
54
Larry Johnsonc591dff2007-12-27 11:28:51 -050055int board_early_init_f(void)
56{
Larry Johnson6433fa22008-03-17 11:10:35 -050057 uint32_t sdr0_pfc1, sdr0_pfc2;
58 uint32_t reg;
Larry Johnsonc591dff2007-12-27 11:28:51 -050059 int eth;
60
Larry Johnson6433fa22008-03-17 11:10:35 -050061#if defined(CONFIG_KORAT_PERMANENT)
62 unsigned mscount;
63
64 extern void korat_branch_absolute(uint32_t addr);
65
66 for (mscount = 0; mscount < CFG_KORAT_MAN_RESET_MS; ++mscount) {
67 udelay(1000);
68 if (gpio_read_in_bit(CFG_GPIO_RESET_PRESSED_)) {
69 /* This call does not return. */
70 korat_branch_absolute(
71 CFG_FLASH1_TOP - 2 * CFG_ENV_SECT_SIZE - 4);
72 }
73 }
74 korat_buzzer(1);
75 while (!gpio_read_in_bit(CFG_GPIO_RESET_PRESSED_))
76 udelay(1000);
77
78 korat_buzzer(0);
79#endif
80
Larry Johnsonc591dff2007-12-27 11:28:51 -050081 mtdcr(ebccfga, xbcfg);
82 mtdcr(ebccfgd, 0xb8400000);
83
Larry Johnson3259eea2008-01-17 08:50:09 -050084 /*
Larry Johnsonc591dff2007-12-27 11:28:51 -050085 * Setup the interrupt controller polarities, triggers, etc.
Larry Johnson3259eea2008-01-17 08:50:09 -050086 */
Larry Johnsonc591dff2007-12-27 11:28:51 -050087 mtdcr(uic0sr, 0xffffffff); /* clear all */
88 mtdcr(uic0er, 0x00000000); /* disable all */
89 mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
90 mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
91 mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
92 mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
93 mtdcr(uic0sr, 0xffffffff); /* clear all */
94
95 mtdcr(uic1sr, 0xffffffff); /* clear all */
96 mtdcr(uic1er, 0x00000000); /* disable all */
97 mtdcr(uic1cr, 0x00000000); /* all non-critical */
98 mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
99 mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
100 mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
101 mtdcr(uic1sr, 0xffffffff); /* clear all */
102
103 mtdcr(uic2sr, 0xffffffff); /* clear all */
104 mtdcr(uic2er, 0x00000000); /* disable all */
105 mtdcr(uic2cr, 0x00000000); /* all non-critical */
106 mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
107 mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
108 mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
109 mtdcr(uic2sr, 0xffffffff); /* clear all */
110
Larry Johnson6433fa22008-03-17 11:10:35 -0500111 /*
112 * Take sim card reader and CF controller out of reset. Also enable PHY
113 * auto-detect until board-specific PHY resets are available.
114 */
115 out_8((u8 *) CFG_CPLD_BASE + 0x02, 0xC0);
Larry Johnsonc591dff2007-12-27 11:28:51 -0500116
117 /* Configure the two Ethernet PHYs. For each PHY, configure for fiber
118 * if the SFP module is present, and for copper if it is not present.
119 */
Larry Johnsonc591dff2007-12-27 11:28:51 -0500120 for (eth = 0; eth < 2; ++eth) {
Lawrence R. Johnson0ddd9692008-01-03 15:02:02 -0500121 if (gpio_read_in_bit(CFG_GPIO_SFP0_PRESENT_ + eth)) {
Larry Johnsonc591dff2007-12-27 11:28:51 -0500122 /* SFP module not present: configure PHY for copper. */
123 /* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */
Larry Johnson6433fa22008-03-17 11:10:35 -0500124 out_8((u8 *) CFG_CPLD_BASE + 0x03,
125 in_8((u8 *) CFG_CPLD_BASE + 0x03) |
Larry Johnsonc591dff2007-12-27 11:28:51 -0500126 0x06 << (4 * eth));
127 } else {
128 /* SFP module present: configure PHY for fiber and
129 enable output */
Lawrence R. Johnson0ddd9692008-01-03 15:02:02 -0500130 gpio_write_bit(CFG_GPIO_PHY0_FIBER_SEL + eth, 1);
131 gpio_write_bit(CFG_GPIO_SFP0_TX_EN_ + eth, 0);
Larry Johnsonc591dff2007-12-27 11:28:51 -0500132 }
133 }
134 /* enable Ethernet: set GPIO45 and GPIO46 to 1 */
Lawrence R. Johnson0ddd9692008-01-03 15:02:02 -0500135 gpio_write_bit(CFG_GPIO_PHY0_EN, 1);
136 gpio_write_bit(CFG_GPIO_PHY1_EN, 1);
Larry Johnsonc591dff2007-12-27 11:28:51 -0500137
Larry Johnson6433fa22008-03-17 11:10:35 -0500138 /* Wait 1 ms, then enable Fiber signal detect to PHYs. */
139 udelay(1000);
140 out_8((u8 *) CFG_CPLD_BASE + 0x03,
141 in_8((u8 *) CFG_CPLD_BASE + 0x03) | 0x88);
142
143 /* select Ethernet (and optionally IIC1) pins */
Larry Johnsonc591dff2007-12-27 11:28:51 -0500144 mfsdr(SDR0_PFC1, sdr0_pfc1);
145 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
Larry Johnson3259eea2008-01-17 08:50:09 -0500146 SDR0_PFC1_SELECT_CONFIG_4;
Larry Johnson6433fa22008-03-17 11:10:35 -0500147#ifdef CONFIG_I2C_MULTI_BUS
148 sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
149#endif
Larry Johnsonc591dff2007-12-27 11:28:51 -0500150 mfsdr(SDR0_PFC2, sdr0_pfc2);
151 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
Larry Johnson3259eea2008-01-17 08:50:09 -0500152 SDR0_PFC2_SELECT_CONFIG_4;
Larry Johnsonc591dff2007-12-27 11:28:51 -0500153 mtsdr(SDR0_PFC2, sdr0_pfc2);
154 mtsdr(SDR0_PFC1, sdr0_pfc1);
155
156 /* PCI arbiter enabled */
157 mfsdr(sdr_pci0, reg);
158 mtsdr(sdr_pci0, 0x80000000 | reg);
159
160 return 0;
161}
162
Larry Johnson6433fa22008-03-17 11:10:35 -0500163/*
164 * The boot flash on CS0 normally has its write-enable pin disabled, and so will
165 * not respond to CFI commands. This routine therefore fills in the flash
166 * information for the boot flash. (The flash at CS1 operates normally.)
167 */
168ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
169{
170 uint32_t addr;
171 int i;
172
173 if (1 != banknum)
174 return 0;
175
176 info->size = CFG_FLASH0_SIZE;
177 info->sector_count = CFG_FLASH0_SIZE / 0x20000;
178 info->flash_id = 0x01000000;
179 info->portwidth = 2;
180 info->chipwidth = 2;
181 info->buffer_size = 32;
182 info->erase_blk_tout = 16384;
183 info->write_tout = 2;
184 info->buffer_write_tout = 5;
185 info->vendor = 2;
186 info->cmd_reset = 0x00F0;
187 info->interface = 2;
188 info->legacy_unlock = 0;
189 info->manufacturer_id = 1;
190 info->device_id = 0x007E;
191
192#if CFG_FLASH0_SIZE == 0x01000000
193 info->device_id2 = 0x2101;
194#elif CFG_FLASH0_SIZE == 0x04000000
195 info->device_id2 = 0x2301;
196#else
197#error Unable to set device_id2 for current CFG_FLASH0_SIZE
198#endif
199
200 info->ext_addr = 0x0040;
201 info->cfi_version = 0x3133;
202 info->cfi_offset = 0x0055;
203 info->addr_unlock1 = 0x00000555;
204 info->addr_unlock2 = 0x000002AA;
205 info->name = "CFI conformant";
206 for (i = 0, addr = -info->size;
207 i < info->sector_count;
208 ++i, addr += 0x20000) {
209 info->start[i] = addr;
210 info->protect[i] = 0x00;
211 }
212 return 1;
213}
214
Larry Johnsonc591dff2007-12-27 11:28:51 -0500215static int man_data_read(unsigned int addr)
216{
217 /*
218 * Read an octet of data from address "addr" in the manufacturer's
219 * information serial EEPROM, or -1 on error.
220 */
221 u8 data[2];
222
223 if (0 != i2c_probe(MAN_DATA_EEPROM_ADDR) ||
224 0 != i2c_read(MAN_DATA_EEPROM_ADDR, addr, 1, data, 1)) {
225 debug("man_data_read(0x%02X) failed\n", addr);
226 return -1;
227 }
228 debug("man_info_read(0x%02X) returned 0x%02X\n", addr, data[0]);
229 return data[0];
230}
231
232static unsigned int man_data_field_addr(unsigned int const field)
233{
234 /*
235 * The manufacturer's information serial EEPROM contains a sequence of
236 * zero-delimited fields. Return the starting address of field "field",
237 * or 0 on error.
238 */
239 unsigned addr, i;
240
241 if (0 == field || 'A' != man_data_read(0) || '\0' != man_data_read(1))
242 /* Only format "A" is currently supported */
243 return 0;
244
245 for (addr = 2, i = 1; i < field && addr < 256; ++addr) {
246 if ('\0' == man_data_read(addr))
247 ++i;
248 }
249 return (addr < 256) ? addr : 0;
250}
251
252static char *man_data_read_field(char s[], unsigned const field,
253 unsigned const length)
254{
255 /*
256 * Place the null-terminated contents of field "field" of length
257 * "length" from the manufacturer's information serial EEPROM into
258 * string "s[length + 1]" and return a pointer to s, or return 0 on
259 * error. In either case the original contents of s[] is not preserved.
260 */
261 unsigned addr, i;
262
263 addr = man_data_field_addr(field);
264 if (0 == addr || addr + length >= 255)
265 return 0;
266
267 for (i = 0; i < length; ++i) {
268 int const c = man_data_read(addr++);
269
270 if (c <= 0)
271 return 0;
272
273 s[i] = (char)c;
274 }
275 if (0 != man_data_read(addr))
276 return 0;
277
278 s[i] = '\0';
279 return s;
280}
281
282static void set_serial_number(void)
283{
284 /*
285 * If the environmental variable "serial#" is not set, try to set it
286 * from the manufacturer's information serial EEPROM.
287 */
Larry Johnson6433fa22008-03-17 11:10:35 -0500288 char s[MAN_INFO_LENGTH + MAN_MAC_ADDR_LENGTH + 2];
Larry Johnsonc591dff2007-12-27 11:28:51 -0500289
Larry Johnson6433fa22008-03-17 11:10:35 -0500290 if (getenv("serial#"))
291 return;
292
293 if (!man_data_read_field(s, MAN_INFO_FIELD, MAN_INFO_LENGTH))
294 return;
295
296 s[MAN_INFO_LENGTH] = '-';
297 if (!man_data_read_field(s + MAN_INFO_LENGTH + 1, MAN_MAC_ADDR_FIELD,
298 MAN_MAC_ADDR_LENGTH))
299 return;
300
301 setenv("serial#", s);
Larry Johnsonc591dff2007-12-27 11:28:51 -0500302}
303
304static void set_mac_addresses(void)
305{
306 /*
307 * If the environmental variables "ethaddr" and/or "eth1addr" are not
308 * set, try to set them from the manufacturer's information serial
309 * EEPROM.
310 */
Larry Johnson6433fa22008-03-17 11:10:35 -0500311
312#if MAN_MAC_ADDR_LENGTH % 2 != 0
313#error MAN_MAC_ADDR_LENGTH must be an even number
314#endif
315
316 char s[(3 * MAN_MAC_ADDR_LENGTH) / 2];
317 char *src;
318 char *dst;
Larry Johnsonc591dff2007-12-27 11:28:51 -0500319
320 if (0 != getenv("ethaddr") && 0 != getenv("eth1addr"))
321 return;
322
Larry Johnson6433fa22008-03-17 11:10:35 -0500323 if (0 == man_data_read_field(s + (MAN_MAC_ADDR_LENGTH / 2) - 1,
324 MAN_MAC_ADDR_FIELD, MAN_MAC_ADDR_LENGTH))
Larry Johnsonc591dff2007-12-27 11:28:51 -0500325 return;
326
Larry Johnson6433fa22008-03-17 11:10:35 -0500327 for (src = s + (MAN_MAC_ADDR_LENGTH / 2) - 1, dst = s; src != dst;) {
328 *dst++ = *src++;
329 *dst++ = *src++;
330 *dst++ = ':';
331 }
Larry Johnsonc591dff2007-12-27 11:28:51 -0500332 if (0 == getenv("ethaddr"))
333 setenv("ethaddr", s);
334
335 if (0 == getenv("eth1addr")) {
Larry Johnson6433fa22008-03-17 11:10:35 -0500336 ++s[((3 * MAN_MAC_ADDR_LENGTH) / 2) - 2];
Larry Johnsonc591dff2007-12-27 11:28:51 -0500337 setenv("eth1addr", s);
338 }
339}
340
Larry Johnsonc591dff2007-12-27 11:28:51 -0500341int misc_init_r(void)
342{
Larry Johnson6433fa22008-03-17 11:10:35 -0500343 uint32_t pbcr;
344 int size_val;
345 uint32_t reg;
Larry Johnsonc591dff2007-12-27 11:28:51 -0500346 unsigned long usb2d0cr = 0;
347 unsigned long usb2phy0cr, usb2h0cr = 0;
348 unsigned long sdr0_pfc1;
Larry Johnson6433fa22008-03-17 11:10:35 -0500349 uint32_t const flash1_size = gd->bd->bi_flashsize - CFG_FLASH0_SIZE;
350 char const *const act = getenv("usbact");
Larry Johnsonc591dff2007-12-27 11:28:51 -0500351
Larry Johnson6433fa22008-03-17 11:10:35 -0500352 /*
353 * Re-do FLASH1 sizing and adjust flash start and offset.
354 */
355 gd->bd->bi_flashstart = CFG_FLASH1_TOP - flash1_size;
Larry Johnsonc591dff2007-12-27 11:28:51 -0500356 gd->bd->bi_flashoffset = 0;
357
Larry Johnson6433fa22008-03-17 11:10:35 -0500358 mtdcr(ebccfga, pb1cr);
Larry Johnsonc591dff2007-12-27 11:28:51 -0500359 pbcr = mfdcr(ebccfgd);
Larry Johnson6433fa22008-03-17 11:10:35 -0500360 size_val = ffs(flash1_size) - 21;
Larry Johnsonc591dff2007-12-27 11:28:51 -0500361 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
Larry Johnson6433fa22008-03-17 11:10:35 -0500362 mtdcr(ebccfga, pb1cr);
Larry Johnsonc591dff2007-12-27 11:28:51 -0500363 mtdcr(ebccfgd, pbcr);
364
365 /*
366 * Re-check to get correct base address
367 */
368 flash_get_size(gd->bd->bi_flashstart, 0);
369
Larry Johnson6433fa22008-03-17 11:10:35 -0500370 /*
371 * Re-do FLASH1 sizing and adjust flash offset to reserve space for
372 * environment
373 */
374 gd->bd->bi_flashoffset =
375 CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - CFG_FLASH1_ADDR;
Larry Johnsonc591dff2007-12-27 11:28:51 -0500376
Larry Johnson6433fa22008-03-17 11:10:35 -0500377 mtdcr(ebccfga, pb1cr);
378 pbcr = mfdcr(ebccfgd);
379 size_val = ffs(gd->bd->bi_flashsize - CFG_FLASH0_SIZE) - 21;
380 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
381 mtdcr(ebccfga, pb1cr);
382 mtdcr(ebccfgd, pbcr);
383
384 /* Monitor protection ON by default */
385#if defined(CONFIG_KORAT_PERMANENT)
386 (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
387 CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
388 flash_info + 1);
389#else
390 (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
391 CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
392 flash_info);
393#endif
Larry Johnsonc591dff2007-12-27 11:28:51 -0500394 /* Env protection ON by default */
Larry Johnson6433fa22008-03-17 11:10:35 -0500395 (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
396 CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
397 flash_info);
Larry Johnson3259eea2008-01-17 08:50:09 -0500398 (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
Larry Johnson6433fa22008-03-17 11:10:35 -0500399 CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
400 flash_info);
Larry Johnsonc591dff2007-12-27 11:28:51 -0500401
402 /*
403 * USB suff...
404 */
405 if (act == NULL || strcmp(act, "hostdev") == 0) {
406 /* SDR Setting */
407 mfsdr(SDR0_PFC1, sdr0_pfc1);
408 mfsdr(SDR0_USB2D0CR, usb2d0cr);
409 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
410 mfsdr(SDR0_USB2H0CR, usb2h0cr);
411
Larry Johnson3259eea2008-01-17 08:50:09 -0500412 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
413 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
414 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
415 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
416 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
417 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
418 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
419 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
420 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
421 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
Larry Johnsonc591dff2007-12-27 11:28:51 -0500422
Larry Johnson3259eea2008-01-17 08:50:09 -0500423 /*
424 * An 8-bit/60MHz interface is the only possible alternative
425 * when connecting the Device to the PHY
426 */
427 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
428 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
Larry Johnsonc591dff2007-12-27 11:28:51 -0500429
Larry Johnson3259eea2008-01-17 08:50:09 -0500430 /*
431 * To enable the USB 2.0 Device function
432 * through the UTMI interface
433 */
434 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
435 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
Larry Johnsonc591dff2007-12-27 11:28:51 -0500436
Larry Johnson3259eea2008-01-17 08:50:09 -0500437 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
438 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
Larry Johnsonc591dff2007-12-27 11:28:51 -0500439
440 mtsdr(SDR0_PFC1, sdr0_pfc1);
441 mtsdr(SDR0_USB2D0CR, usb2d0cr);
442 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
443 mtsdr(SDR0_USB2H0CR, usb2h0cr);
444
Larry Johnson3259eea2008-01-17 08:50:09 -0500445 /* clear resets */
Larry Johnsonc591dff2007-12-27 11:28:51 -0500446 udelay(1000);
447 mtsdr(SDR0_SRST1, 0x00000000);
448 udelay(1000);
449 mtsdr(SDR0_SRST0, 0x00000000);
450
451 printf("USB: Host(int phy) Device(ext phy)\n");
452
453 } else if (strcmp(act, "dev") == 0) {
454 /*-------------------PATCH-------------------------------*/
455 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
456
Larry Johnson3259eea2008-01-17 08:50:09 -0500457 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
458 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
459 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
460 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
461 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
462 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
463 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
464 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
Larry Johnsonc591dff2007-12-27 11:28:51 -0500465 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
466
467 udelay(1000);
468 mtsdr(SDR0_SRST1, 0x672c6000);
469
470 udelay(1000);
471 mtsdr(SDR0_SRST0, 0x00000080);
472
473 udelay(1000);
474 mtsdr(SDR0_SRST1, 0x60206000);
475
476 *(unsigned int *)(0xe0000350) = 0x00000001;
477
478 udelay(1000);
479 mtsdr(SDR0_SRST1, 0x60306000);
480 /*-------------------PATCH-------------------------------*/
481
482 /* SDR Setting */
483 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
484 mfsdr(SDR0_USB2H0CR, usb2h0cr);
485 mfsdr(SDR0_USB2D0CR, usb2d0cr);
486 mfsdr(SDR0_PFC1, sdr0_pfc1);
487
Larry Johnson3259eea2008-01-17 08:50:09 -0500488 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
489 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
490 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
491 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
492 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
493 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
494 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
495 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
496 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
497 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
Larry Johnsonc591dff2007-12-27 11:28:51 -0500498
Larry Johnson3259eea2008-01-17 08:50:09 -0500499 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
500 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
Larry Johnsonc591dff2007-12-27 11:28:51 -0500501
Larry Johnson3259eea2008-01-17 08:50:09 -0500502 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
503 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
Larry Johnsonc591dff2007-12-27 11:28:51 -0500504
Larry Johnson3259eea2008-01-17 08:50:09 -0500505 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
506 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
Larry Johnsonc591dff2007-12-27 11:28:51 -0500507
508 mtsdr(SDR0_USB2H0CR, usb2h0cr);
509 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
510 mtsdr(SDR0_USB2D0CR, usb2d0cr);
511 mtsdr(SDR0_PFC1, sdr0_pfc1);
512
Larry Johnson3259eea2008-01-17 08:50:09 -0500513 /* clear resets */
Larry Johnsonc591dff2007-12-27 11:28:51 -0500514 udelay(1000);
515 mtsdr(SDR0_SRST1, 0x00000000);
516 udelay(1000);
517 mtsdr(SDR0_SRST0, 0x00000000);
518
519 printf("USB: Device(int phy)\n");
520 }
521
Larry Johnson3259eea2008-01-17 08:50:09 -0500522 mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
Larry Johnsonc591dff2007-12-27 11:28:51 -0500523 reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
524 mtsdr(SDR0_SRST1, reg);
525
526 /*
527 * Clear PLB4A0_ACR[WRP]
528 * This fix will make the MAL burst disabling patch for the Linux
529 * EMAC driver obsolete.
530 */
531 reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
532 mtdcr(plb4_acr, reg);
533
534 set_serial_number();
535 set_mac_addresses();
Larry Johnson6433fa22008-03-17 11:10:35 -0500536 gpio_write_bit(CFG_GPIO_ATMEGA_RESET_, 1);
537
Larry Johnsonc591dff2007-12-27 11:28:51 -0500538 return 0;
539}
540
541int checkboard(void)
542{
543 char const *const s = getenv("serial#");
544 u8 const rev = in_8((u8 *) CFG_CPLD_BASE + 0);
Larry Johnsonc591dff2007-12-27 11:28:51 -0500545
546 printf("Board: Korat, Rev. %X", rev);
Larry Johnson6433fa22008-03-17 11:10:35 -0500547 if (s)
Larry Johnsonc591dff2007-12-27 11:28:51 -0500548 printf(", serial# %s", s);
549
Larry Johnson6433fa22008-03-17 11:10:35 -0500550 printf(".\n Ethernet PHY 0: ");
Lawrence R. Johnson0ddd9692008-01-03 15:02:02 -0500551 if (gpio_read_out_bit(CFG_GPIO_PHY0_FIBER_SEL))
Larry Johnsonc591dff2007-12-27 11:28:51 -0500552 printf("fiber");
553 else
554 printf("copper");
555
556 printf(", PHY 1: ");
Lawrence R. Johnson0ddd9692008-01-03 15:02:02 -0500557 if (gpio_read_out_bit(CFG_GPIO_PHY1_FIBER_SEL))
Larry Johnsonc591dff2007-12-27 11:28:51 -0500558 printf("fiber");
559 else
560 printf("copper");
561
562 printf(".\n");
Larry Johnson6433fa22008-03-17 11:10:35 -0500563#if defined(CONFIG_KORAT_PERMANENT)
564 printf(" Executing permanent copy of U-Boot.\n");
565#endif
566 return 0;
Larry Johnsonc591dff2007-12-27 11:28:51 -0500567}
568
569#if defined(CFG_DRAM_TEST)
570int testdram(void)
571{
572 unsigned long *mem = (unsigned long *)0;
573 const unsigned long kend = (1024 / sizeof(unsigned long));
574 unsigned long k, n;
575
576 mtmsr(0);
577
578 /* TODO: find correct size of SDRAM */
579 for (k = 0; k < CFG_MBYTES_SDRAM;
580 ++k, mem += (1024 / sizeof(unsigned long))) {
581 if ((k & 1023) == 0)
582 printf("%3d MB\r", k / 1024);
583
584 memset(mem, 0xaaaaaaaa, 1024);
585 for (n = 0; n < kend; ++n) {
586 if (mem[n] != 0xaaaaaaaa) {
587 printf("SDRAM test fails at: %08x\n",
588 (uint) & mem[n]);
589 return 1;
590 }
591 }
592
593 memset(mem, 0x55555555, 1024);
594 for (n = 0; n < kend; ++n) {
595 if (mem[n] != 0x55555555) {
596 printf("SDRAM test fails at: %08x\n",
597 (uint) & mem[n]);
598 return 1;
599 }
600 }
601 }
602 printf("SDRAM test passes\n");
603 return 0;
604}
605#endif /* defined(CFG_DRAM_TEST) */
606
Larry Johnson3259eea2008-01-17 08:50:09 -0500607/*
608 * pci_pre_init
Larry Johnsonc591dff2007-12-27 11:28:51 -0500609 *
Larry Johnson3259eea2008-01-17 08:50:09 -0500610 * This routine is called just prior to registering the hose and gives
611 * the board the opportunity to check things. Returning a value of zero
612 * indicates that things are bad & PCI initialization should be aborted.
Larry Johnsonc591dff2007-12-27 11:28:51 -0500613 *
Larry Johnson3259eea2008-01-17 08:50:09 -0500614 * Different boards may wish to customize the pci controller structure
615 * (add regions, override default access routines, etc) or perform
616 * certain pre-initialization actions.
617 */
Larry Johnsonc591dff2007-12-27 11:28:51 -0500618#if defined(CONFIG_PCI)
619int pci_pre_init(struct pci_controller *hose)
620{
621 unsigned long addr;
622
Larry Johnson3259eea2008-01-17 08:50:09 -0500623 /*
624 * Set priority for all PLB3 devices to 0.
625 * Set PLB3 arbiter to fair mode.
626 */
Larry Johnsonc591dff2007-12-27 11:28:51 -0500627 mfsdr(sdr_amp1, addr);
628 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
629 addr = mfdcr(plb3_acr);
630 mtdcr(plb3_acr, addr | 0x80000000);
631
Larry Johnson3259eea2008-01-17 08:50:09 -0500632 /*
633 * Set priority for all PLB4 devices to 0.
634 */
Larry Johnsonc591dff2007-12-27 11:28:51 -0500635 mfsdr(sdr_amp0, addr);
636 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
637 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
638 mtdcr(plb4_acr, addr);
639
Larry Johnson3259eea2008-01-17 08:50:09 -0500640 /*
641 * Set Nebula PLB4 arbiter to fair mode.
642 */
Larry Johnsonc591dff2007-12-27 11:28:51 -0500643 /* Segment0 */
644 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
645 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
646 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
647 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
648 mtdcr(plb0_acr, addr);
649
650 /* Segment1 */
651 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
652 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
653 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
654 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
655 mtdcr(plb1_acr, addr);
656
657 return 1;
658}
659#endif /* defined(CONFIG_PCI) */
660
Larry Johnson3259eea2008-01-17 08:50:09 -0500661/*
662 * pci_target_init
Larry Johnsonc591dff2007-12-27 11:28:51 -0500663 *
Larry Johnson3259eea2008-01-17 08:50:09 -0500664 * The bootstrap configuration provides default settings for the pci
665 * inbound map (PIM). But the bootstrap config choices are limited and
666 * may not be sufficient for a given board.
667 */
Larry Johnsonc591dff2007-12-27 11:28:51 -0500668#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
669void pci_target_init(struct pci_controller *hose)
670{
Larry Johnson3259eea2008-01-17 08:50:09 -0500671 /*
Larry Johnsonc591dff2007-12-27 11:28:51 -0500672 * Set up Direct MMIO registers
Larry Johnson3259eea2008-01-17 08:50:09 -0500673 */
674 /*
675 * PowerPC440EPX PCI Master configuration.
676 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
Larry Johnson6433fa22008-03-17 11:10:35 -0500677 * PLB address 0x80000000-0xBFFFFFFF
678 * ==> PCI address 0x80000000-0xBFFFFFFF
Larry Johnson3259eea2008-01-17 08:50:09 -0500679 * Use byte reversed out routines to handle endianess.
680 * Make this region non-prefetchable.
681 */
682 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
683 /* - disabled b4 setting */
Larry Johnsonc591dff2007-12-27 11:28:51 -0500684 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
Larry Johnson6433fa22008-03-17 11:10:35 -0500685 out32r(PCIX0_PMM0PCILA,
686 CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
Larry Johnsonc591dff2007-12-27 11:28:51 -0500687 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
Larry Johnson3259eea2008-01-17 08:50:09 -0500688 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
689 /* and enable region */
Larry Johnsonc591dff2007-12-27 11:28:51 -0500690
Larry Johnson3259eea2008-01-17 08:50:09 -0500691 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
692 /* - disabled b4 setting */
Larry Johnson6433fa22008-03-17 11:10:35 -0500693 out32r(PCIX0_PMM1LA,
694 CFG_PCI_MEMBASE + 0x20000000); /* PMM0 Local Address */
695 out32r(PCIX0_PMM1PCILA,
696 CFG_PCI_MEMBASE + 0x20000000); /* PMM0 PCI Low Address */
Larry Johnsonc591dff2007-12-27 11:28:51 -0500697 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
Larry Johnson3259eea2008-01-17 08:50:09 -0500698 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
699 /* and enable region */
Larry Johnsonc591dff2007-12-27 11:28:51 -0500700
701 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
Larry Johnson3259eea2008-01-17 08:50:09 -0500702 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
703 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
704 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
Larry Johnsonc591dff2007-12-27 11:28:51 -0500705
Larry Johnson3259eea2008-01-17 08:50:09 -0500706 /*
Larry Johnsonc591dff2007-12-27 11:28:51 -0500707 * Set up Configuration registers
Larry Johnson3259eea2008-01-17 08:50:09 -0500708 */
Larry Johnsonc591dff2007-12-27 11:28:51 -0500709
710 /* Program the board's subsystem id/vendor id */
711 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
712 CFG_PCI_SUBSYS_VENDORID);
713 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
714
715 /* Configure command register as bus master */
716 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
717
718 /* 240nS PCI clock */
719 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
720
721 /* No error reporting */
722 pci_write_config_word(0, PCI_ERREN, 0);
723
724 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
725
Larry Johnson3259eea2008-01-17 08:50:09 -0500726 /*
727 * Set up Configuration registers for on-board NEC uPD720101 USB
728 * controller.
729 */
Larry Johnsonc591dff2007-12-27 11:28:51 -0500730 pci_write_config_dword(PCI_BDF(0x0, 0xC, 0x0), 0xE4, 0x00000020);
731}
732#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
733
Larry Johnsonc591dff2007-12-27 11:28:51 -0500734#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
735void pci_master_init(struct pci_controller *hose)
736{
737 unsigned short temp_short;
738
Larry Johnson3259eea2008-01-17 08:50:09 -0500739 /*
740 * Write the PowerPC440 EP PCI Configuration regs.
741 * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
742 * Enable PowerPC440 EP to act as a PCI memory target (PTM).
743 */
Larry Johnsonc591dff2007-12-27 11:28:51 -0500744 pci_read_config_word(0, PCI_COMMAND, &temp_short);
745 pci_write_config_word(0, PCI_COMMAND,
746 temp_short | PCI_COMMAND_MASTER |
747 PCI_COMMAND_MEMORY);
748}
749#endif
750
Larry Johnson3259eea2008-01-17 08:50:09 -0500751/*
752 * is_pci_host
Larry Johnsonc591dff2007-12-27 11:28:51 -0500753 *
Larry Johnson3259eea2008-01-17 08:50:09 -0500754 * This routine is called to determine if a pci scan should be
755 * performed. With various hardware environments (especially cPCI and
756 * PPMC) it's insufficient to depend on the state of the arbiter enable
757 * bit in the strap register, or generic host/adapter assumptions.
Larry Johnsonc591dff2007-12-27 11:28:51 -0500758 *
Larry Johnson3259eea2008-01-17 08:50:09 -0500759 * Rather than hard-code a bad assumption in the general 440 code, the
760 * 440 pci code requires the board to decide at runtime.
Larry Johnsonc591dff2007-12-27 11:28:51 -0500761 *
Larry Johnson3259eea2008-01-17 08:50:09 -0500762 * Return 0 for adapter mode, non-zero for host (monarch) mode.
763 */
Larry Johnsonc591dff2007-12-27 11:28:51 -0500764#if defined(CONFIG_PCI)
765int is_pci_host(struct pci_controller *hose)
766{
767 /* Korat is always configured as host. */
768 return (1);
769}
Larry Johnson3259eea2008-01-17 08:50:09 -0500770#endif /* defined(CONFIG_PCI) */
Larry Johnsonc591dff2007-12-27 11:28:51 -0500771
772#if defined(CONFIG_POST)
773/*
774 * Returns 1 if keys pressed to start the power-on long-running tests
775 * Called from board_init_f().
776 */
777int post_hotkeys_pressed(void)
778{
Larry Johnson3259eea2008-01-17 08:50:09 -0500779 return 0; /* No hotkeys supported */
Larry Johnsonc591dff2007-12-27 11:28:51 -0500780}
Larry Johnson3259eea2008-01-17 08:50:09 -0500781#endif /* CONFIG_POST */