blob: 26b532ad6931d7ed5790afc8664f11fc10618d98 [file] [log] [blame]
Rafal Jaworowski692519b2006-08-10 12:43:17 +02001/*
2 * Copyright (c) 2005 Cisco Systems. All rights reserved.
3 * Roland Dreier <rolandd@cisco.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Rafal Jaworowski692519b2006-08-10 12:43:17 +02006 */
7
Stefan Roese026f7112007-10-03 07:48:09 +02008#ifndef __4XX_PCIE_H
9#define __4XX_PCIE_H
Rafal Jaworowski692519b2006-08-10 12:43:17 +020010
Stefan Roeseb36df562010-09-09 19:18:00 +020011#include <asm/ppc4xx.h>
Stefan Roese5cd01302008-04-28 11:37:14 +020012#include <pci.h>
Stefan Roese24bfedb2008-04-22 12:20:32 +020013
Rafal Jaworowski692519b2006-08-10 12:43:17 +020014#define DCRN_SDR0_CFGADDR 0x00e
15#define DCRN_SDR0_CFGDATA 0x00f
16
Stefan Roese03d344b2007-10-03 10:38:09 +020017#if defined(CONFIG_440SPE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020018#define CONFIG_SYS_PCIE_NR_PORTS 3
Stefan Roese97923772007-10-05 09:18:23 +020019
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020020#define CONFIG_SYS_PCIE_ADDR_HIGH 0x0000000d
Stefan Roese97923772007-10-05 09:18:23 +020021
Rafal Jaworowski692519b2006-08-10 12:43:17 +020022#define DCRN_PCIE0_BASE 0x100
23#define DCRN_PCIE1_BASE 0x120
24#define DCRN_PCIE2_BASE 0x140
Stefan Roese97923772007-10-05 09:18:23 +020025
26#define PCIE0_SDR 0x300
27#define PCIE1_SDR 0x340
28#define PCIE2_SDR 0x370
Stefan Roese03d344b2007-10-03 10:38:09 +020029#endif
30
Stefan Roese999ecd52008-03-11 15:07:10 +010031#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020032#define CONFIG_SYS_PCIE_NR_PORTS 2
Stefan Roese999ecd52008-03-11 15:07:10 +010033
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034#define CONFIG_SYS_PCIE_ADDR_HIGH 0x0000000d
Stefan Roese999ecd52008-03-11 15:07:10 +010035
36#define DCRN_PCIE0_BASE 0x100
37#define DCRN_PCIE1_BASE 0x120
38
39#define PCIE0_SDR 0x300
40#define PCIE1_SDR 0x340
41#endif
42
Stefan Roese03d344b2007-10-03 10:38:09 +020043#if defined(CONFIG_405EX)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044#define CONFIG_SYS_PCIE_NR_PORTS 2
Stefan Roese97923772007-10-05 09:18:23 +020045
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046#define CONFIG_SYS_PCIE_ADDR_HIGH 0x00000000
Stefan Roese97923772007-10-05 09:18:23 +020047
Stefan Roese03d344b2007-10-03 10:38:09 +020048#define DCRN_PCIE0_BASE 0x040
49#define DCRN_PCIE1_BASE 0x060
Stefan Roese97923772007-10-05 09:18:23 +020050
51#define PCIE0_SDR 0x400
52#define PCIE1_SDR 0x440
Stefan Roese03d344b2007-10-03 10:38:09 +020053#endif
54
Rafal Jaworowski692519b2006-08-10 12:43:17 +020055#define PCIE0 DCRN_PCIE0_BASE
56#define PCIE1 DCRN_PCIE1_BASE
57#define PCIE2 DCRN_PCIE2_BASE
58
59#define DCRN_PEGPL_CFGBAH(base) (base + 0x00)
60#define DCRN_PEGPL_CFGBAL(base) (base + 0x01)
61#define DCRN_PEGPL_CFGMSK(base) (base + 0x02)
62#define DCRN_PEGPL_MSGBAH(base) (base + 0x03)
63#define DCRN_PEGPL_MSGBAL(base) (base + 0x04)
64#define DCRN_PEGPL_MSGMSK(base) (base + 0x05)
65#define DCRN_PEGPL_OMR1BAH(base) (base + 0x06)
66#define DCRN_PEGPL_OMR1BAL(base) (base + 0x07)
67#define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08)
68#define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09)
69#define DCRN_PEGPL_REGBAH(base) (base + 0x12)
70#define DCRN_PEGPL_REGBAL(base) (base + 0x13)
71#define DCRN_PEGPL_REGMSK(base) (base + 0x14)
72#define DCRN_PEGPL_SPECIAL(base) (base + 0x15)
Grzegorz Bernacki15ee4732007-09-07 17:46:18 +020073#define DCRN_PEGPL_CFG(base) (base + 0x16)
Rafal Jaworowski692519b2006-08-10 12:43:17 +020074
75/*
76 * System DCRs (SDRs)
77 */
78#define PESDR0_PLLLCT1 0x03a0
79#define PESDR0_PLLLCT2 0x03a1
80#define PESDR0_PLLLCT3 0x03a2
81
Stefan Roese999ecd52008-03-11 15:07:10 +010082/* common regs, at for all 4xx with PCIe core */
Stefan Roese03d344b2007-10-03 10:38:09 +020083#define SDRN_PESDR_UTLSET1(n) (sdr_base(n) + 0x00)
84#define SDRN_PESDR_UTLSET2(n) (sdr_base(n) + 0x01)
85#define SDRN_PESDR_DLPSET(n) (sdr_base(n) + 0x02)
86#define SDRN_PESDR_LOOP(n) (sdr_base(n) + 0x03)
87#define SDRN_PESDR_RCSSET(n) (sdr_base(n) + 0x04)
88#define SDRN_PESDR_RCSSTS(n) (sdr_base(n) + 0x05)
89
90#if defined(CONFIG_440SPE)
91#define SDRN_PESDR_HSSL0SET1(n) (sdr_base(n) + 0x06)
92#define SDRN_PESDR_HSSL0SET2(n) (sdr_base(n) + 0x07)
93#define SDRN_PESDR_HSSL0STS(n) (sdr_base(n) + 0x08)
94#define SDRN_PESDR_HSSL1SET1(n) (sdr_base(n) + 0x09)
95#define SDRN_PESDR_HSSL1SET2(n) (sdr_base(n) + 0x0a)
96#define SDRN_PESDR_HSSL1STS(n) (sdr_base(n) + 0x0b)
97#define SDRN_PESDR_HSSL2SET1(n) (sdr_base(n) + 0x0c)
98#define SDRN_PESDR_HSSL2SET2(n) (sdr_base(n) + 0x0d)
99#define SDRN_PESDR_HSSL2STS(n) (sdr_base(n) + 0x0e)
100#define SDRN_PESDR_HSSL3SET1(n) (sdr_base(n) + 0x0f)
101#define SDRN_PESDR_HSSL3SET2(n) (sdr_base(n) + 0x10)
102#define SDRN_PESDR_HSSL3STS(n) (sdr_base(n) + 0x11)
103
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200104#define PESDR0_UTLSET1 0x0300
105#define PESDR0_UTLSET2 0x0301
106#define PESDR0_DLPSET 0x0302
107#define PESDR0_LOOP 0x0303
108#define PESDR0_RCSSET 0x0304
109#define PESDR0_RCSSTS 0x0305
110#define PESDR0_HSSL0SET1 0x0306
111#define PESDR0_HSSL0SET2 0x0307
112#define PESDR0_HSSL0STS 0x0308
113#define PESDR0_HSSL1SET1 0x0309
114#define PESDR0_HSSL1SET2 0x030a
115#define PESDR0_HSSL1STS 0x030b
116#define PESDR0_HSSL2SET1 0x030c
117#define PESDR0_HSSL2SET2 0x030d
118#define PESDR0_HSSL2STS 0x030e
119#define PESDR0_HSSL3SET1 0x030f
120#define PESDR0_HSSL3SET2 0x0310
121#define PESDR0_HSSL3STS 0x0311
122#define PESDR0_HSSL4SET1 0x0312
123#define PESDR0_HSSL4SET2 0x0313
124#define PESDR0_HSSL4STS 0x0314
125#define PESDR0_HSSL5SET1 0x0315
126#define PESDR0_HSSL5SET2 0x0316
127#define PESDR0_HSSL5STS 0x0317
128#define PESDR0_HSSL6SET1 0x0318
129#define PESDR0_HSSL6SET2 0x0319
130#define PESDR0_HSSL6STS 0x031a
131#define PESDR0_HSSL7SET1 0x031b
132#define PESDR0_HSSL7SET2 0x031c
133#define PESDR0_HSSL7STS 0x031d
134#define PESDR0_HSSCTLSET 0x031e
135#define PESDR0_LANE_ABCD 0x031f
136#define PESDR0_LANE_EFGH 0x0320
137
138#define PESDR1_UTLSET1 0x0340
139#define PESDR1_UTLSET2 0x0341
140#define PESDR1_DLPSET 0x0342
141#define PESDR1_LOOP 0x0343
142#define PESDR1_RCSSET 0x0344
143#define PESDR1_RCSSTS 0x0345
144#define PESDR1_HSSL0SET1 0x0346
145#define PESDR1_HSSL0SET2 0x0347
146#define PESDR1_HSSL0STS 0x0348
147#define PESDR1_HSSL1SET1 0x0349
148#define PESDR1_HSSL1SET2 0x034a
149#define PESDR1_HSSL1STS 0x034b
150#define PESDR1_HSSL2SET1 0x034c
151#define PESDR1_HSSL2SET2 0x034d
152#define PESDR1_HSSL2STS 0x034e
153#define PESDR1_HSSL3SET1 0x034f
154#define PESDR1_HSSL3SET2 0x0350
155#define PESDR1_HSSL3STS 0x0351
156#define PESDR1_HSSCTLSET 0x0352
157#define PESDR1_LANE_ABCD 0x0353
158
159#define PESDR2_UTLSET1 0x0370
160#define PESDR2_UTLSET2 0x0371
161#define PESDR2_DLPSET 0x0372
162#define PESDR2_LOOP 0x0373
163#define PESDR2_RCSSET 0x0374
164#define PESDR2_RCSSTS 0x0375
165#define PESDR2_HSSL0SET1 0x0376
166#define PESDR2_HSSL0SET2 0x0377
167#define PESDR2_HSSL0STS 0x0378
168#define PESDR2_HSSL1SET1 0x0379
169#define PESDR2_HSSL1SET2 0x037a
170#define PESDR2_HSSL1STS 0x037b
171#define PESDR2_HSSL2SET1 0x037c
172#define PESDR2_HSSL2SET2 0x037d
173#define PESDR2_HSSL2STS 0x037e
174#define PESDR2_HSSL3SET1 0x037f
175#define PESDR2_HSSL3SET2 0x0380
176#define PESDR2_HSSL3STS 0x0381
177#define PESDR2_HSSCTLSET 0x0382
178#define PESDR2_LANE_ABCD 0x0383
179
Stefan Roese03d344b2007-10-03 10:38:09 +0200180#elif defined(CONFIG_405EX)
181
182#define SDRN_PESDR_PHYSET1(n) (sdr_base(n) + 0x06)
183#define SDRN_PESDR_PHYSET2(n) (sdr_base(n) + 0x07)
184#define SDRN_PESDR_BIST(n) (sdr_base(n) + 0x08)
185#define SDRN_PESDR_LPB(n) (sdr_base(n) + 0x0b)
186#define SDRN_PESDR_PHYSTA(n) (sdr_base(n) + 0x0c)
187
188#define PESDR0_UTLSET1 0x0400
189#define PESDR0_UTLSET2 0x0401
190#define PESDR0_DLPSET 0x0402
191#define PESDR0_LOOP 0x0403
192#define PESDR0_RCSSET 0x0404
193#define PESDR0_RCSSTS 0x0405
194#define PESDR0_PHYSET1 0x0406
195#define PESDR0_PHYSET2 0x0407
196#define PESDR0_BIST 0x0408
197#define PESDR0_LPB 0x040B
198#define PESDR0_PHYSTA 0x040C
199
200#define PESDR1_UTLSET1 0x0440
201#define PESDR1_UTLSET2 0x0441
202#define PESDR1_DLPSET 0x0442
203#define PESDR1_LOOP 0x0443
204#define PESDR1_RCSSET 0x0444
205#define PESDR1_RCSSTS 0x0445
206#define PESDR1_PHYSET1 0x0446
207#define PESDR1_PHYSET2 0x0447
208#define PESDR1_BIST 0x0448
209#define PESDR1_LPB 0x044B
210#define PESDR1_PHYSTA 0x044C
211
Stefan Roese999ecd52008-03-11 15:07:10 +0100212#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
213
214#define PESDR0_L0BIST 0x0308 /* PE0 L0 built in self test */
215#define PESDR0_L0BISTSTS 0x0309 /* PE0 L0 built in self test status */
216#define PESDR0_L0CDRCTL 0x030A /* PE0 L0 CDR control */
217#define PESDR0_L0DRV 0x030B /* PE0 L0 drive */
218#define PESDR0_L0REC 0x030C /* PE0 L0 receiver */
219#define PESDR0_L0LPB 0x030D /* PE0 L0 loopback */
220#define PESDR0_L0CLK 0x030E /* PE0 L0 clocking */
221#define PESDR0_PHY_CTL_RST 0x030F /* PE0 PHY control reset */
222#define PESDR0_RSTSTA 0x0310 /* PE0 reset status */
223#define PESDR0_OBS 0x0311 /* PE0 observation register */
224#define PESDR0_L0ERRC 0x0320 /* PE0 L0 error counter */
225
226#define PESDR1_L0BIST 0x0348 /* PE1 L0 built in self test */
227#define PESDR1_L1BIST 0x0349 /* PE1 L1 built in self test */
228#define PESDR1_L2BIST 0x034A /* PE1 L2 built in self test */
229#define PESDR1_L3BIST 0x034B /* PE1 L3 built in self test */
230#define PESDR1_L0BISTSTS 0x034C /* PE1 L0 built in self test status */
231#define PESDR1_L1BISTSTS 0x034D /* PE1 L1 built in self test status */
232#define PESDR1_L2BISTSTS 0x034E /* PE1 L2 built in self test status */
233#define PESDR1_L3BISTSTS 0x034F /* PE1 L3 built in self test status */
234#define PESDR1_L0CDRCTL 0x0350 /* PE1 L0 CDR control */
235#define PESDR1_L1CDRCTL 0x0351 /* PE1 L1 CDR control */
236#define PESDR1_L2CDRCTL 0x0352 /* PE1 L2 CDR control */
237#define PESDR1_L3CDRCTL 0x0353 /* PE1 L3 CDR control */
238#define PESDR1_L0DRV 0x0354 /* PE1 L0 drive */
239#define PESDR1_L1DRV 0x0355 /* PE1 L1 drive */
240#define PESDR1_L2DRV 0x0356 /* PE1 L2 drive */
241#define PESDR1_L3DRV 0x0357 /* PE1 L3 drive */
242#define PESDR1_L0REC 0x0358 /* PE1 L0 receiver */
243#define PESDR1_L1REC 0x0359 /* PE1 L1 receiver */
244#define PESDR1_L2REC 0x035A /* PE1 L2 receiver */
245#define PESDR1_L3REC 0x035B /* PE1 L3 receiver */
246#define PESDR1_L0LPB 0x035C /* PE1 L0 loopback */
247#define PESDR1_L1LPB 0x035D /* PE1 L1 loopback */
248#define PESDR1_L2LPB 0x035E /* PE1 L2 loopback */
249#define PESDR1_L3LPB 0x035F /* PE1 L3 loopback */
250#define PESDR1_L0CLK 0x0360 /* PE1 L0 clocking */
251#define PESDR1_L1CLK 0x0361 /* PE1 L1 clocking */
252#define PESDR1_L2CLK 0x0362 /* PE1 L2 clocking */
253#define PESDR1_L3CLK 0x0363 /* PE1 L3 clocking */
254#define PESDR1_PHY_CTL_RST 0x0364 /* PE1 PHY control reset */
255#define PESDR1_RSTSTA 0x0365 /* PE1 reset status */
256#define PESDR1_OBS 0x0366 /* PE1 observation register */
257#define PESDR1_L0ERRC 0x0368 /* PE1 L0 error counter */
258#define PESDR1_L1ERRC 0x0369 /* PE1 L1 error counter */
259#define PESDR1_L2ERRC 0x036A /* PE1 L2 error counter */
260#define PESDR1_L3ERRC 0x036B /* PE1 L3 error counter */
261#define PESDR0_IHS1 0x036C /* PE interrupt handler interfact setting 1 */
262#define PESDR0_IHS2 0x036D /* PE interrupt handler interfact setting 2 */
263
Stefan Roese03d344b2007-10-03 10:38:09 +0200264#endif
265
Stefan Roese999ecd52008-03-11 15:07:10 +0100266/* SDR Bit Mappings */
267#define PESDRx_RCSSET_HLDPLB 0x10000000
268#define PESDRx_RCSSET_RSTGU 0x01000000
269#define PESDRx_RCSSET_RDY 0x00100000
270#define PESDRx_RCSSET_RSTDL 0x00010000
271#define PESDRx_RCSSET_RSTPYN 0x00001000
272
273#define PESDRx_RCSSTS_PLBIDL 0x10000000
274#define PESDRx_RCSSTS_HRSTRQ 0x01000000
275#define PESDRx_RCSSTS_PGRST 0x00100000
276#define PESDRx_RCSSTS_VC0ACT 0x00010000
277#define PESDRx_RCSSTS_BMEN 0x00000100
278
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200279/*
280 * UTL register offsets
281 */
Stefan Roesef31d38b2007-11-16 14:16:54 +0100282#define PEUTL_PBCTL 0x00
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200283#define PEUTL_PBBSZ 0x20
284#define PEUTL_OPDBSZ 0x68
285#define PEUTL_IPHBSZ 0x70
286#define PEUTL_IPDBSZ 0x78
287#define PEUTL_OUTTR 0x90
288#define PEUTL_INTR 0x98
289#define PEUTL_PCTL 0xa0
Stefan Roesef31d38b2007-11-16 14:16:54 +0100290#define PEUTL_RCSTA 0xb0
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200291#define PEUTL_RCIRQEN 0xb8
292
293/*
294 * Config space register offsets
295 */
296#define PECFG_BAR0LMPA 0x210
297#define PECFG_BAR0HMPA 0x214
Stefan Roese2b393b02006-08-29 08:05:15 +0200298#define PECFG_BAR1MPA 0x218
Stefan Roese5cb4af42007-10-18 07:39:38 +0200299#define PECFG_BAR2LMPA 0x220
300#define PECFG_BAR2HMPA 0x224
Stefan Roese2b393b02006-08-29 08:05:15 +0200301
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200302#define PECFG_PIMEN 0x33c
303#define PECFG_PIM0LAL 0x340
304#define PECFG_PIM0LAH 0x344
Grzegorz Bernackic9240982007-07-31 18:51:48 +0200305#define PECFG_PIM1LAL 0x348
306#define PECFG_PIM1LAH 0x34c
Stefan Roese2b393b02006-08-29 08:05:15 +0200307#define PECFG_PIM01SAL 0x350
308#define PECFG_PIM01SAH 0x354
309
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200310#define PECFG_POM0LAL 0x380
311#define PECFG_POM0LAH 0x384
312
313#define SDR_READ(offset) ({\
314 mtdcr(DCRN_SDR0_CFGADDR, offset); \
315 mfdcr(DCRN_SDR0_CFGDATA);})
316
317#define SDR_WRITE(offset, data) ({\
318 mtdcr(DCRN_SDR0_CFGADDR, offset); \
319 mtdcr(DCRN_SDR0_CFGDATA,data);})
320
Grzegorz Bernacki15ee4732007-09-07 17:46:18 +0200321#define GPL_DMER_MASK_DISA 0x02000000
Grzegorz Bernackic9240982007-07-31 18:51:48 +0200322
Stefan Roese97923772007-10-05 09:18:23 +0200323#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
324#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
325
Stefan Roesed4cb2d12007-10-13 16:43:23 +0200326/*
327 * Prototypes
328 */
Stefan Roese026f7112007-10-03 07:48:09 +0200329int ppc4xx_init_pcie(void);
330int ppc4xx_init_pcie_rootport(int port);
Stefan Roese03d344b2007-10-03 10:38:09 +0200331int ppc4xx_init_pcie_endport(int port);
Stefan Roese026f7112007-10-03 07:48:09 +0200332void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port);
333int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200334int pcie_hose_scan(struct pci_controller *hose, int bus);
Stefan Roese026f7112007-10-03 07:48:09 +0200335
Stefan Roesed4cb2d12007-10-13 16:43:23 +0200336/*
337 * Function to determine root port or endport from env variable.
338 */
339static inline int is_end_point(int port)
340{
Stefan Roese5cb4af42007-10-18 07:39:38 +0200341 char s[10], *tk;
342 char *pcie_mode = getenv("pcie_mode");
Stefan Roesed4cb2d12007-10-13 16:43:23 +0200343
Stefan Roese5cb4af42007-10-18 07:39:38 +0200344 if (pcie_mode == NULL)
345 return 0;
346
347 strcpy(s, pcie_mode);
Stefan Roesed4cb2d12007-10-13 16:43:23 +0200348 tk = strtok(s, ":");
349
350 switch (port) {
351 case 0:
352 if (tk != NULL) {
353 if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
354 return 1;
355 else
356 return 0;
357 }
358 else
359 return 0;
360
361 case 1:
362 tk = strtok(NULL, ":");
363 if (tk != NULL) {
364 if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
365 return 1;
366 else
367 return 0;
368 }
369 else
370 return 0;
371
372 case 2:
373 tk = strtok(NULL, ":");
374 if (tk != NULL)
375 tk = strtok(NULL, ":");
376 if (tk != NULL) {
377 if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
378 return 1;
379 else
380 return 0;
381 }
382 else
383 return 0;
384 }
385
386 return 0;
387}
388
Stefan Roese24bfedb2008-04-22 12:20:32 +0200389#if defined(PCIE0_SDR)
Stefan Roese03d344b2007-10-03 10:38:09 +0200390static inline u32 sdr_base(int port)
391{
392 switch (port) {
393 default: /* to satisfy compiler */
394 case 0:
395 return PCIE0_SDR;
396 case 1:
397 return PCIE1_SDR;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#if CONFIG_SYS_PCIE_NR_PORTS > 2
Stefan Roese03d344b2007-10-03 10:38:09 +0200399 case 2:
400 return PCIE2_SDR;
401#endif
402 }
403}
Stefan Roese24bfedb2008-04-22 12:20:32 +0200404#endif /* defined(PCIE0_SDR) */
Stefan Roese03d344b2007-10-03 10:38:09 +0200405
Stefan Roese026f7112007-10-03 07:48:09 +0200406#endif /* __4XX_PCIE_H */