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wdenkaffae2b2002-08-17 09:36:01 +00001/*
2 * (C) Copyright 2002 SIXNET, dge@sixnetio.com.
3 *
wdenkec4c5442004-02-09 23:12:24 +00004 * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
5 * Stephan Linz <linz@li-pro.net>
6 *
wdenkaffae2b2002-08-17 09:36:01 +00007 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*
wdenkec4c5442004-02-09 23:12:24 +000027 * Date & Time support for DS1306 RTC using SPI:
28 *
29 * - SXNI855T: it uses its own soft SPI here in this file
30 * - all other: use the external spi_xfer() function
31 * (see include/spi.h)
wdenkaffae2b2002-08-17 09:36:01 +000032 */
33
34#include <common.h>
35#include <command.h>
36#include <rtc.h>
wdenkec4c5442004-02-09 23:12:24 +000037#include <spi.h>
wdenkaffae2b2002-08-17 09:36:01 +000038
39#if defined(CONFIG_RTC_DS1306) && (CONFIG_COMMANDS & CFG_CMD_DATE)
40
wdenkec4c5442004-02-09 23:12:24 +000041#define RTC_SECONDS 0x00
42#define RTC_MINUTES 0x01
43#define RTC_HOURS 0x02
44#define RTC_DAY_OF_WEEK 0x03
45#define RTC_DATE_OF_MONTH 0x04
46#define RTC_MONTH 0x05
47#define RTC_YEAR 0x06
48
49#define RTC_SECONDS_ALARM0 0x07
50#define RTC_MINUTES_ALARM0 0x08
51#define RTC_HOURS_ALARM0 0x09
52#define RTC_DAY_OF_WEEK_ALARM0 0x0a
53
54#define RTC_SECONDS_ALARM1 0x0b
55#define RTC_MINUTES_ALARM1 0x0c
56#define RTC_HOURS_ALARM1 0x0d
57#define RTC_DAY_OF_WEEK_ALARM1 0x0e
58
59#define RTC_CONTROL 0x0f
60#define RTC_STATUS 0x10
61#define RTC_TRICKLE_CHARGER 0x11
62
63#define RTC_USER_RAM_BASE 0x20
64
65/*
66 * External table of chip select functions (see the appropriate board
67 * support for the actual definition of the table).
68 */
69extern spi_chipsel_type spi_chipsel[];
70extern int spi_chipsel_cnt;
71
72static unsigned int bin2bcd (unsigned int n);
73static unsigned char bcd2bin (unsigned char c);
wdenkec4c5442004-02-09 23:12:24 +000074
wdenkec4c5442004-02-09 23:12:24 +000075/* ************************************************************************* */
76#ifdef CONFIG_SXNI855T /* !!! SHOULD BE CHANGED TO NEW CODE !!! */
77
78static void soft_spi_send (unsigned char n);
79static unsigned char soft_spi_read (void);
80static void init_spi (void);
wdenkaffae2b2002-08-17 09:36:01 +000081
82/*-----------------------------------------------------------------------
83 * Definitions
84 */
85
86#define PB_SPISCK 0x00000002 /* PB 30 */
87#define PB_SPIMOSI 0x00000004 /* PB 29 */
88#define PB_SPIMISO 0x00000008 /* PB 28 */
89#define PB_SPI_CE 0x00010000 /* PB 15 */
90
91/* ------------------------------------------------------------------------- */
92
93/* read clock time from DS1306 and return it in *tmp */
wdenkec4c5442004-02-09 23:12:24 +000094void rtc_get (struct rtc_time *tmp)
wdenkaffae2b2002-08-17 09:36:01 +000095{
wdenkec4c5442004-02-09 23:12:24 +000096 volatile immap_t *immap = (immap_t *) CFG_IMMR;
97 unsigned char spi_byte; /* Data Byte */
wdenkaffae2b2002-08-17 09:36:01 +000098
wdenkec4c5442004-02-09 23:12:24 +000099 init_spi (); /* set port B for software SPI */
wdenkaffae2b2002-08-17 09:36:01 +0000100
wdenkec4c5442004-02-09 23:12:24 +0000101 /* Now we can enable the DS1306 RTC */
102 immap->im_cpm.cp_pbdat |= PB_SPI_CE;
103 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000104
wdenkec4c5442004-02-09 23:12:24 +0000105 /* Shift out the address (0) of the time in the Clock Chip */
106 soft_spi_send (0);
wdenkaffae2b2002-08-17 09:36:01 +0000107
wdenkec4c5442004-02-09 23:12:24 +0000108 /* Put the clock readings into the rtc_time structure */
109 tmp->tm_sec = bcd2bin (soft_spi_read ()); /* Read seconds */
110 tmp->tm_min = bcd2bin (soft_spi_read ()); /* Read minutes */
wdenkaffae2b2002-08-17 09:36:01 +0000111
wdenkec4c5442004-02-09 23:12:24 +0000112 /* Hours are trickier */
113 spi_byte = soft_spi_read (); /* Read Hours into temporary value */
114 if (spi_byte & 0x40) {
115 /* 12 hour mode bit is set (time is in 1-12 format) */
116 if (spi_byte & 0x20) {
117 /* since PM we add 11 to get 0-23 for hours */
118 tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) + 11;
119 } else {
120 /* since AM we subtract 1 to get 0-23 for hours */
121 tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) - 1;
122 }
123 } else {
124 /* Otherwise, 0-23 hour format */
125 tmp->tm_hour = (bcd2bin (spi_byte & 0x3F));
wdenkaffae2b2002-08-17 09:36:01 +0000126 }
wdenkaffae2b2002-08-17 09:36:01 +0000127
wdenkec4c5442004-02-09 23:12:24 +0000128 soft_spi_read (); /* Read and discard Day of week */
129 tmp->tm_mday = bcd2bin (soft_spi_read ()); /* Read Day of the Month */
130 tmp->tm_mon = bcd2bin (soft_spi_read ()); /* Read Month */
wdenkaffae2b2002-08-17 09:36:01 +0000131
wdenkec4c5442004-02-09 23:12:24 +0000132 /* Read Year and convert to this century */
133 tmp->tm_year = bcd2bin (soft_spi_read ()) + 2000;
wdenkaffae2b2002-08-17 09:36:01 +0000134
wdenkec4c5442004-02-09 23:12:24 +0000135 /* Now we can disable the DS1306 RTC */
136 immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */
137 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000138
wdenkec4c5442004-02-09 23:12:24 +0000139 GregorianDay (tmp); /* Determine the day of week */
wdenkaffae2b2002-08-17 09:36:01 +0000140
wdenkec4c5442004-02-09 23:12:24 +0000141 debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
142 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
143 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
wdenkaffae2b2002-08-17 09:36:01 +0000144}
145
146/* ------------------------------------------------------------------------- */
147
148/* set clock time in DS1306 RTC and in MPC8xx RTC */
wdenkec4c5442004-02-09 23:12:24 +0000149void rtc_set (struct rtc_time *tmp)
wdenkaffae2b2002-08-17 09:36:01 +0000150{
wdenkec4c5442004-02-09 23:12:24 +0000151 volatile immap_t *immap = (immap_t *) CFG_IMMR;
wdenkaffae2b2002-08-17 09:36:01 +0000152
wdenkec4c5442004-02-09 23:12:24 +0000153 init_spi (); /* set port B for software SPI */
wdenkaffae2b2002-08-17 09:36:01 +0000154
wdenkec4c5442004-02-09 23:12:24 +0000155 /* Now we can enable the DS1306 RTC */
156 immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */
157 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000158
wdenkec4c5442004-02-09 23:12:24 +0000159 /* First disable write protect in the clock chip control register */
160 soft_spi_send (0x8F); /* send address of the control register */
161 soft_spi_send (0x00); /* send control register contents */
wdenkaffae2b2002-08-17 09:36:01 +0000162
wdenkec4c5442004-02-09 23:12:24 +0000163 /* Now disable the DS1306 to terminate the write */
164 immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;
165 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000166
wdenkec4c5442004-02-09 23:12:24 +0000167 /* Now enable the DS1306 to initiate a new write */
168 immap->im_cpm.cp_pbdat |= PB_SPI_CE;
169 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000170
wdenkec4c5442004-02-09 23:12:24 +0000171 /* Next, send the address of the clock time write registers */
172 soft_spi_send (0x80); /* send address of the first time register */
wdenkaffae2b2002-08-17 09:36:01 +0000173
wdenkec4c5442004-02-09 23:12:24 +0000174 /* Use Burst Mode to send all of the time data to the clock */
175 bin2bcd (tmp->tm_sec);
176 soft_spi_send (bin2bcd (tmp->tm_sec)); /* Send Seconds */
177 soft_spi_send (bin2bcd (tmp->tm_min)); /* Send Minutes */
178 soft_spi_send (bin2bcd (tmp->tm_hour)); /* Send Hour */
179 soft_spi_send (bin2bcd (tmp->tm_wday)); /* Send Day of the Week */
180 soft_spi_send (bin2bcd (tmp->tm_mday)); /* Send Day of Month */
181 soft_spi_send (bin2bcd (tmp->tm_mon)); /* Send Month */
182 soft_spi_send (bin2bcd (tmp->tm_year - 2000)); /* Send Year */
wdenkaffae2b2002-08-17 09:36:01 +0000183
wdenkec4c5442004-02-09 23:12:24 +0000184 /* Now we can disable the Clock chip to terminate the burst write */
185 immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */
186 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000187
wdenkec4c5442004-02-09 23:12:24 +0000188 /* Now we can enable the Clock chip to initiate a new write */
189 immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */
190 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000191
wdenkec4c5442004-02-09 23:12:24 +0000192 /* First we Enable write protect in the clock chip control register */
193 soft_spi_send (0x8F); /* send address of the control register */
194 soft_spi_send (0x40); /* send out Control Register contents */
wdenkaffae2b2002-08-17 09:36:01 +0000195
wdenkec4c5442004-02-09 23:12:24 +0000196 /* Now disable the DS1306 */
197 immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */
198 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000199
wdenkec4c5442004-02-09 23:12:24 +0000200 /* Set standard MPC8xx clock to the same time so Linux will
201 * see the time even if it doesn't have a DS1306 clock driver.
202 * This helps with experimenting with standard kernels.
203 */
204 {
205 ulong tim;
wdenkaffae2b2002-08-17 09:36:01 +0000206
wdenkec4c5442004-02-09 23:12:24 +0000207 tim = mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday,
208 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
wdenkaffae2b2002-08-17 09:36:01 +0000209
wdenkec4c5442004-02-09 23:12:24 +0000210 immap->im_sitk.sitk_rtck = KAPWR_KEY;
211 immap->im_sit.sit_rtc = tim;
212 }
wdenkaffae2b2002-08-17 09:36:01 +0000213
wdenkec4c5442004-02-09 23:12:24 +0000214 debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
215 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
216 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
wdenkaffae2b2002-08-17 09:36:01 +0000217}
218
219/* ------------------------------------------------------------------------- */
220
221/* Initialize Port B for software SPI */
wdenkec4c5442004-02-09 23:12:24 +0000222static void init_spi (void)
223{
224 volatile immap_t *immap = (immap_t *) CFG_IMMR;
wdenkaffae2b2002-08-17 09:36:01 +0000225
wdenkec4c5442004-02-09 23:12:24 +0000226 /* Force output pins to begin at logic 0 */
227 immap->im_cpm.cp_pbdat &= ~(PB_SPI_CE | PB_SPIMOSI | PB_SPISCK);
wdenkaffae2b2002-08-17 09:36:01 +0000228
wdenkec4c5442004-02-09 23:12:24 +0000229 /* Set these 3 signals as outputs */
230 immap->im_cpm.cp_pbdir |= (PB_SPIMOSI | PB_SPI_CE | PB_SPISCK);
wdenkaffae2b2002-08-17 09:36:01 +0000231
wdenkec4c5442004-02-09 23:12:24 +0000232 immap->im_cpm.cp_pbdir &= ~PB_SPIMISO; /* Make MISO pin an input */
233 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000234}
235
236/* ------------------------------------------------------------------------- */
237
238/* NOTE: soft_spi_send() assumes that the I/O lines are configured already */
wdenkec4c5442004-02-09 23:12:24 +0000239static void soft_spi_send (unsigned char n)
wdenkaffae2b2002-08-17 09:36:01 +0000240{
wdenkec4c5442004-02-09 23:12:24 +0000241 volatile immap_t *immap = (immap_t *) CFG_IMMR;
242 unsigned char bitpos; /* bit position to receive */
243 unsigned char i; /* Loop Control */
wdenkaffae2b2002-08-17 09:36:01 +0000244
wdenkec4c5442004-02-09 23:12:24 +0000245 /* bit position to send, start with most significant bit */
246 bitpos = 0x80;
wdenkaffae2b2002-08-17 09:36:01 +0000247
wdenkec4c5442004-02-09 23:12:24 +0000248 /* Send 8 bits to software SPI */
249 for (i = 0; i < 8; i++) { /* Loop for 8 bits */
250 immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */
wdenkaffae2b2002-08-17 09:36:01 +0000251
wdenkec4c5442004-02-09 23:12:24 +0000252 if (n & bitpos)
253 immap->im_cpm.cp_pbdat |= PB_SPIMOSI; /* Set MOSI to 1 */
254 else
255 immap->im_cpm.cp_pbdat &= ~PB_SPIMOSI; /* Set MOSI to 0 */
256 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000257
wdenkec4c5442004-02-09 23:12:24 +0000258 immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */
259 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000260
wdenkec4c5442004-02-09 23:12:24 +0000261 bitpos >>= 1; /* Shift for next bit position */
262 }
wdenkaffae2b2002-08-17 09:36:01 +0000263}
264
265/* ------------------------------------------------------------------------- */
266
267/* NOTE: soft_spi_read() assumes that the I/O lines are configured already */
wdenkec4c5442004-02-09 23:12:24 +0000268static unsigned char soft_spi_read (void)
wdenkaffae2b2002-08-17 09:36:01 +0000269{
wdenkec4c5442004-02-09 23:12:24 +0000270 volatile immap_t *immap = (immap_t *) CFG_IMMR;
wdenkaffae2b2002-08-17 09:36:01 +0000271
wdenkec4c5442004-02-09 23:12:24 +0000272 unsigned char spi_byte = 0; /* Return value, assume success */
273 unsigned char bitpos; /* bit position to receive */
274 unsigned char i; /* Loop Control */
wdenkaffae2b2002-08-17 09:36:01 +0000275
wdenkec4c5442004-02-09 23:12:24 +0000276 /* bit position to receive, start with most significant bit */
277 bitpos = 0x80;
wdenkaffae2b2002-08-17 09:36:01 +0000278
wdenkec4c5442004-02-09 23:12:24 +0000279 /* Read 8 bits here */
280 for (i = 0; i < 8; i++) { /* Do 8 bits in loop */
281 immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */
282 udelay (10);
283 if (immap->im_cpm.cp_pbdat & PB_SPIMISO) /* Get a bit of data */
284 spi_byte |= bitpos; /* Set data accordingly */
285 immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */
286 udelay (10);
287 bitpos >>= 1; /* Shift for next bit position */
288 }
wdenkaffae2b2002-08-17 09:36:01 +0000289
wdenkec4c5442004-02-09 23:12:24 +0000290 return spi_byte; /* Return the byte read */
wdenkaffae2b2002-08-17 09:36:01 +0000291}
292
293/* ------------------------------------------------------------------------- */
294
wdenkec4c5442004-02-09 23:12:24 +0000295void rtc_reset (void)
296{
297 return; /* nothing to do */
298}
299
300#else /* not CONFIG_SXNI855T */
301/* ************************************************************************* */
302
wdenk3f85ce22004-02-23 16:11:30 +0000303static unsigned char rtc_read (unsigned char reg);
304static void rtc_write (unsigned char reg, unsigned char val);
305
wdenkec4c5442004-02-09 23:12:24 +0000306/* read clock time from DS1306 and return it in *tmp */
307void rtc_get (struct rtc_time *tmp)
308{
309 unsigned char sec, min, hour, mday, wday, mon, year;
310
311 sec = rtc_read (RTC_SECONDS);
312 min = rtc_read (RTC_MINUTES);
313 hour = rtc_read (RTC_HOURS);
314 mday = rtc_read (RTC_DATE_OF_MONTH);
315 wday = rtc_read (RTC_DAY_OF_WEEK);
316 mon = rtc_read (RTC_MONTH);
317 year = rtc_read (RTC_YEAR);
318
319 debug ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
320 "hr: %02x min: %02x sec: %02x\n",
321 year, mon, mday, wday, hour, min, sec);
322 debug ("Alarms[0]: wday: %02x hour: %02x min: %02x sec: %02x\n",
323 rtc_read (RTC_DAY_OF_WEEK_ALARM0),
324 rtc_read (RTC_HOURS_ALARM0),
325 rtc_read (RTC_MINUTES_ALARM0), rtc_read (RTC_SECONDS_ALARM0));
326 debug ("Alarms[1]: wday: %02x hour: %02x min: %02x sec: %02x\n",
327 rtc_read (RTC_DAY_OF_WEEK_ALARM1),
328 rtc_read (RTC_HOURS_ALARM1),
329 rtc_read (RTC_MINUTES_ALARM1), rtc_read (RTC_SECONDS_ALARM1));
330
331 tmp->tm_sec = bcd2bin (sec & 0x7F); /* convert Seconds */
332 tmp->tm_min = bcd2bin (min & 0x7F); /* convert Minutes */
333
334 /* convert Hours */
335 tmp->tm_hour = (hour & 0x40)
336 ? ((hour & 0x20) /* 12 hour mode */
337 ? bcd2bin (hour & 0x1F) + 11 /* PM */
338 : bcd2bin (hour & 0x1F) - 1 /* AM */
339 )
340 : bcd2bin (hour & 0x3F); /* 24 hour mode */
341
342 tmp->tm_mday = bcd2bin (mday & 0x3F); /* convert Day of the Month */
343 tmp->tm_mon = bcd2bin (mon & 0x1F); /* convert Month */
344 tmp->tm_year = bcd2bin (year) + 2000; /* convert Year */
345 tmp->tm_wday = bcd2bin (wday & 0x07) - 1; /* convert Day of the Week */
346 tmp->tm_yday = 0;
347 tmp->tm_isdst = 0;
348
349 debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
350 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
351 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
352}
353
354/* ------------------------------------------------------------------------- */
355
356/* set clock time from *tmp in DS1306 RTC */
357void rtc_set (struct rtc_time *tmp)
358{
359 debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
360 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
361 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
362
wdenkec4c5442004-02-09 23:12:24 +0000363 rtc_write (RTC_SECONDS, bin2bcd (tmp->tm_sec));
Wolfgang Denkda4849f2006-05-03 01:04:58 +0200364 rtc_write (RTC_MINUTES, bin2bcd (tmp->tm_min));
365 rtc_write (RTC_HOURS, bin2bcd (tmp->tm_hour));
366 rtc_write (RTC_DAY_OF_WEEK, bin2bcd (tmp->tm_wday + 1));
367 rtc_write (RTC_DATE_OF_MONTH, bin2bcd (tmp->tm_mday));
368 rtc_write (RTC_MONTH, bin2bcd (tmp->tm_mon));
369 rtc_write (RTC_YEAR, bin2bcd (tmp->tm_year - 2000));
wdenkec4c5442004-02-09 23:12:24 +0000370}
371
372/* ------------------------------------------------------------------------- */
373
374/* reset the DS1306 */
375void rtc_reset (void)
376{
377 /* clear the control register */
378 rtc_write (RTC_CONTROL, 0x00); /* 1st step: reset WP */
379 rtc_write (RTC_CONTROL, 0x00); /* 2nd step: reset 1Hz, AIE1, AIE0 */
380
381 /* reset all alarms */
382 rtc_write (RTC_SECONDS_ALARM0, 0x00);
383 rtc_write (RTC_SECONDS_ALARM1, 0x00);
384 rtc_write (RTC_MINUTES_ALARM0, 0x00);
385 rtc_write (RTC_MINUTES_ALARM1, 0x00);
386 rtc_write (RTC_HOURS_ALARM0, 0x00);
387 rtc_write (RTC_HOURS_ALARM1, 0x00);
388 rtc_write (RTC_DAY_OF_WEEK_ALARM0, 0x00);
389 rtc_write (RTC_DAY_OF_WEEK_ALARM1, 0x00);
390}
391
392/* ------------------------------------------------------------------------- */
393
394static unsigned char rtc_read (unsigned char reg)
395{
396 unsigned char dout[2]; /* SPI Output Data Bytes */
397 unsigned char din[2]; /* SPI Input Data Bytes */
398
399 dout[0] = reg;
400
401 if (spi_xfer (spi_chipsel[CFG_SPI_RTC_DEVID], 16, dout, din) != 0) {
402 return 0;
403 } else {
404 return din[1];
405 }
406}
407
408/* ------------------------------------------------------------------------- */
409
410static void rtc_write (unsigned char reg, unsigned char val)
411{
412 unsigned char dout[2]; /* SPI Output Data Bytes */
413 unsigned char din[2]; /* SPI Input Data Bytes */
414
415 dout[0] = 0x80 | reg;
416 dout[1] = val;
417
418 spi_xfer (spi_chipsel[CFG_SPI_RTC_DEVID], 16, dout, din);
419}
420
421#endif /* end of code exclusion (see #ifdef CONFIG_SXNI855T above) */
422
423/* ------------------------------------------------------------------------- */
424
425static unsigned char bcd2bin (unsigned char n)
426{
427 return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F));
428}
429
430/* ------------------------------------------------------------------------- */
431
432static unsigned int bin2bcd (unsigned int n)
433{
434 return (((n / 10) << 4) | (n % 10));
435}
436/* ------------------------------------------------------------------------- */
437
wdenkaffae2b2002-08-17 09:36:01 +0000438#endif