blob: dc7444d1cc77206a1b010bfdadcae345ec31b15e [file] [log] [blame]
Tom Warrenefc05ae2011-01-27 10:58:07 +00001/*
Tom Warren52a8b822012-05-22 12:19:25 +00002 * (C) Copyright 2010-2012
Tom Warrenefc05ae2011-01-27 10:58:07 +00003 * NVIDIA Corporation <www.nvidia.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
Allen Martin00a27492012-08-31 08:30:00 +000024#ifndef __TEGRA20_COMMON_H
25#define __TEGRA20_COMMON_H
Tom Warrenefc05ae2011-01-27 10:58:07 +000026#include <asm/sizes.h>
Marek Vasut51926d52012-09-23 17:41:25 +020027#include <linux/stringify.h>
Simon Glass649d0ff2012-04-02 13:19:03 +000028
29/*
Tom Warrenefc05ae2011-01-27 10:58:07 +000030 * High Level Configuration Options
31 */
32#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
Allen Martin00a27492012-08-31 08:30:00 +000033#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */
Allen Martin7e5fd8f2012-08-31 08:30:02 +000034#define CONFIG_TEGRA /* which is a Tegra generic machine */
Aneesh Ve47f2db2011-06-16 23:30:48 +000035#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
Tom Warrenefc05ae2011-01-27 10:58:07 +000036
Anton staaf96d21232011-10-03 13:54:58 +000037#define CONFIG_SYS_CACHELINE_SIZE 32
38
Tom Warren150c2492012-09-19 15:50:56 -070039#include <asm/arch/tegra.h> /* get chip and board defs */
Tom Warrenefc05ae2011-01-27 10:58:07 +000040
41/*
42 * Display CPU and Board information
43 */
44#define CONFIG_DISPLAY_CPUINFO
45#define CONFIG_DISPLAY_BOARDINFO
46
Tom Warrenefc05ae2011-01-27 10:58:07 +000047#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
Grant Likely2fa8ca92011-03-28 09:59:07 +000048#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
Tom Warrenefc05ae2011-01-27 10:58:07 +000049
Tom Warren29f3e3f2012-09-04 17:00:24 -070050#ifdef CONFIG_TEGRA_LP0
Simon Glass649d0ff2012-04-02 13:19:03 +000051#define TEGRA_LP0_ADDR 0x1C406000
52#define TEGRA_LP0_SIZE 0x2000
53#define TEGRA_LP0_VEC \
Marek Vasut51926d52012-09-23 17:41:25 +020054 "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
55 "@" __stringify(TEGRA_LP0_ADDR) " "
Simon Glass649d0ff2012-04-02 13:19:03 +000056#else
57#define TEGRA_LP0_VEC
58#endif
59
Tom Warrenefc05ae2011-01-27 10:58:07 +000060/* Environment */
Stephen Warren0a7bec72012-05-22 09:21:55 +000061#define CONFIG_ENV_VARS_UBOOT_CONFIG
Simon Glass9dd79fd2011-11-05 04:46:48 +000062#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */
Tom Warrenefc05ae2011-01-27 10:58:07 +000063
64/*
65 * Size of malloc() pool
66 */
67#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
68
69/*
70 * PllX Configuration
71 */
72#define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */
73
74/*
75 * NS16550 Configuration
76 */
77#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
78
79#define CONFIG_SYS_NS16550
80#define CONFIG_SYS_NS16550_SERIAL
81#define CONFIG_SYS_NS16550_REG_SIZE (-4)
82#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
83
84/*
85 * select serial console configuration
86 */
87#define CONFIG_CONS_INDEX 1
88
89/* allow to overwrite serial and ethaddr */
90#define CONFIG_ENV_OVERWRITE
91#define CONFIG_BAUDRATE 115200
92#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
93 115200}
94
Simon Glass02910912012-02-27 10:52:51 +000095/*
96 * This parameter affects a TXFILLTUNING field that controls how much data is
97 * sent to the latency fifo before it is sent to the wire. Without this
98 * parameter, the default (2) causes occasional Data Buffer Errors in OUT
99 * packets depending on the buffer address and size.
100 */
101#define CONFIG_USB_EHCI_TXFIFO_THRESH 10
102#define CONFIG_EHCI_IS_TDI
103#define CONFIG_EHCI_DCACHE
104
Allen Martin00a27492012-08-31 08:30:00 +0000105/* Total I2C ports on Tegra20 */
Simon Glassc3600332012-02-03 15:13:59 +0000106#define TEGRA_I2C_NUM_CONTROLLERS 4
107
Tom Warrenefc05ae2011-01-27 10:58:07 +0000108/* include default commands */
109#include <config_cmd_default.h>
Stephen Warren01ca2862012-09-25 13:32:26 +0000110#define CONFIG_PARTITION_UUIDS
111#define CONFIG_CMD_PART
Tom Warrenefc05ae2011-01-27 10:58:07 +0000112
113/* remove unused commands */
114#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
115#undef CONFIG_CMD_FPGA /* FPGA configuration support */
116#undef CONFIG_CMD_IMI
117#undef CONFIG_CMD_IMLS
118#undef CONFIG_CMD_NFS /* NFS support */
119#undef CONFIG_CMD_NET /* network support */
120
121/* turn on command-line edit/hist/auto */
122#define CONFIG_CMDLINE_EDITING
123#define CONFIG_COMMAND_HISTORY
Mike Frysingered0fc4b2011-10-26 00:19:58 +0000124#define CONFIG_AUTO_COMPLETE
Tom Warrenefc05ae2011-01-27 10:58:07 +0000125
126#define CONFIG_SYS_NO_FLASH
127
Simon Glass4120c272012-04-17 09:01:36 +0000128/* Environment information, boards can override if required */
129#define CONFIG_CONSOLE_MUX
130#define CONFIG_SYS_CONSOLE_IS_IN_ENV
Tom Warren29f3e3f2012-09-04 17:00:24 -0700131#define TEGRA_DEVICE_SETTINGS "stdin=serial\0" \
132 "stdout=serial\0" \
133 "stderr=serial\0"
Simon Glass4120c272012-04-17 09:01:36 +0000134
Tom Warrenefc05ae2011-01-27 10:58:07 +0000135#define CONFIG_LOADADDR 0x408000 /* def. location for kernel */
136#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
137
138/*
139 * Miscellaneous configurable options
140 */
141#define CONFIG_SYS_LONGHELP /* undef to save memory */
142#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
Tom Warrenefc05ae2011-01-27 10:58:07 +0000143#define CONFIG_SYS_PROMPT V_PROMPT
144/*
145 * Increasing the size of the IO buffer as default nfsargs size is more
146 * than 256 and so it is not possible to edit it
147 */
148#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */
149/* Print Buffer Size */
150#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
151 sizeof(CONFIG_SYS_PROMPT) + 16)
152#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
153/* Boot Argument Buffer Size */
154#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
155
Tom Warren29f3e3f2012-09-04 17:00:24 -0700156#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
Tom Warrenefc05ae2011-01-27 10:58:07 +0000157#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
158
159#define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */
160#define CONFIG_SYS_HZ 1000
161
Tom Warrenefc05ae2011-01-27 10:58:07 +0000162#define CONFIG_STACKBASE 0x2800000 /* 40MB */
Tom Warrenefc05ae2011-01-27 10:58:07 +0000163
164/*-----------------------------------------------------------------------
165 * Physical Memory Map
166 */
167#define CONFIG_NR_DRAM_BANKS 1
Tom Warren29f3e3f2012-09-04 17:00:24 -0700168#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
Tom Warrenefc05ae2011-01-27 10:58:07 +0000169#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
170
Allen Martin12b7b702012-08-31 08:30:12 +0000171#define CONFIG_SYS_TEXT_BASE 0x0010c000
Tom Warrenefc05ae2011-01-27 10:58:07 +0000172#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
173
174#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
175#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
176#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
177 CONFIG_SYS_INIT_RAM_SIZE - \
178 GENERATED_GBL_DATA_SIZE)
179
Tom Warren52a8b822012-05-22 12:19:25 +0000180#define CONFIG_TEGRA_GPIO
Tom Warrenf84d64d2011-06-17 06:27:29 +0000181#define CONFIG_CMD_GPIO
Stephen Warren9cd3f3a2012-06-04 09:23:55 +0000182#define CONFIG_CMD_ENTERRCM
Stephen Warrendd8ab952012-06-13 09:55:11 +0000183#define CONFIG_CMD_BOOTZ
Allen Martin12b7b702012-08-31 08:30:12 +0000184
185/* Defines for SPL */
186#define CONFIG_SPL
187#define CONFIG_SPL_NAND_SIMPLE
188#define CONFIG_SPL_TEXT_BASE 0x00108000
189#define CONFIG_SPL_MAX_SIZE 0x00004000
190#define CONFIG_SYS_SPL_MALLOC_START 0x00090000
191#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
192#define CONFIG_SPL_STACK 0x000ffffc
193
194#define CONFIG_SPL_LIBCOMMON_SUPPORT
195#define CONFIG_SPL_LIBGENERIC_SUPPORT
196#define CONFIG_SPL_SERIAL_SUPPORT
197#define CONFIG_SPL_GPIO_SUPPORT
198#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds"
199
Simon Glass0dd84082012-07-29 20:53:30 +0000200#define CONFIG_SYS_NAND_SELF_INIT
201
Allen Martin00a27492012-08-31 08:30:00 +0000202#endif /* __TEGRA20_COMMON_H */