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Wolfgang Denk1a459662013-07-08 09:37:19 +02001TABILITY or FITNESS FO04-2007 Freescale Semiconductor, Inc.
TsiChung Liew6d33c6a2008-07-23 17:11:47 -05002 * Hayden Fraser (Hayden.Fraser@freescale.com)
3 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
TsiChung Liew6d33c6a2008-07-23 17:11:47 -05005 */
6
7#ifndef _M5253DEMO_H
8#define _M5253DEMO_H
9
10#define CONFIG_MCF52x2 /* define processor family */
11#define CONFIG_M5253 /* define processor type */
12#define CONFIG_M5253DEMO /* define board type */
13
14#define CONFIG_MCFTMR
15
16#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020017#define CONFIG_SYS_UART_PORT (0)
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050018#define CONFIG_BAUDRATE 115200
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050019
20#undef CONFIG_WATCHDOG /* disable watchdog */
21
22#define CONFIG_BOOTDELAY 5
23
24/* Configuration for environment
25 * Environment is embedded in u-boot in the second sector of the flash
26 */
27#ifdef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020028# define CONFIG_ENV_OFFSET 0x4000
29# define CONFIG_ENV_SECT_SIZE 0x1000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020030# define CONFIG_ENV_IS_IN_FLASH 1
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050031#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020032# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020033# define CONFIG_ENV_SECT_SIZE 0x1000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020034# define CONFIG_ENV_IS_IN_FLASH 1
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050035#endif
36
37/*
38 * Command line configuration.
39 */
40#include <config_cmd_default.h>
41
TsiChung Liewdd9f0542010-03-11 22:12:53 -060042#define CONFIG_CMD_CACHE
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050043#define CONFIG_CMD_LOADB
44#define CONFIG_CMD_LOADS
45#define CONFIG_CMD_EXT2
46#define CONFIG_CMD_FAT
47#define CONFIG_CMD_IDE
48#define CONFIG_CMD_MEMORY
49#define CONFIG_CMD_MISC
50#define CONFIG_CMD_PING
51
52#ifdef CONFIG_CMD_IDE
53/* ATA */
54# define CONFIG_DOS_PARTITION
55# define CONFIG_MAC_PARTITION
56# define CONFIG_IDE_RESET 1
57# define CONFIG_IDE_PREINIT 1
58# define CONFIG_ATAPI
59# undef CONFIG_LBA48
60
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061# define CONFIG_SYS_IDE_MAXBUS 1
62# define CONFIG_SYS_IDE_MAXDEVICE 2
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050063
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064# define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
65# define CONFIG_SYS_ATA_IDE0_OFFSET 0
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050066
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067# define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
68# define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
69# define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
70# define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050071#endif
72
73#define CONFIG_DRIVER_DM9000
74#ifdef CONFIG_DRIVER_DM9000
TsiChung Liew012522f2008-10-21 10:03:07 +000075# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300)
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050076# define DM9000_IO CONFIG_DM9000_BASE
77# define DM9000_DATA (CONFIG_DM9000_BASE + 4)
78# undef CONFIG_DM9000_DEBUG
Jason Jinf73e7d62011-08-19 10:18:15 +080079# define CONFIG_DM9000_BYTE_SWAPPED
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050080
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050081# define CONFIG_OVERWRITE_ETHADDR_ONCE
82
83# define CONFIG_EXTRA_ENV_SETTINGS \
84 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +020085 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050086 "loadaddr=10000\0" \
87 "u-boot=u-boot.bin\0" \
88 "load=tftp ${loadaddr) ${u-boot}\0" \
89 "upd=run load; run prog\0" \
TsiChung Liewac265f72010-03-10 11:56:36 -060090 "prog=prot off 0xff800000 0xff82ffff;" \
91 "era 0xff800000 0xff82ffff;" \
TsiChung Liewf26a2472010-03-15 19:39:21 -050092 "cp.b ${loadaddr} 0xff800000 ${filesize};" \
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050093 "save\0" \
94 ""
95#endif
96
97#define CONFIG_HOSTNAME M5253DEMO
98
TsiChung Lieweec567a2008-08-19 03:01:19 +060099/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200100#define CONFIG_SYS_I2C
101#define CONFIG_SYS_I2C_FSL
102#define CONFIG_SYS_FSL_I2C_SPEED 80000
103#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
104#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
106#define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
107#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
108#define CONFIG_SYS_I2C_PINMUX_SET (0)
TsiChung Lieweec567a2008-08-19 03:01:19 +0600109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_PROMPT "=> "
111#define CONFIG_SYS_LONGHELP /* undef to save memory */
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500112
113#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500115#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500117#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
119#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
120#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_LOAD_ADDR 0x00100000
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_MEMTEST_START 0x400
125#define CONFIG_SYS_MEMTEST_END 0x380000
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_HZ 1000
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
130#define CONFIG_SYS_FAST_CLK
131#ifdef CONFIG_SYS_FAST_CLK
132# define CONFIG_SYS_PLLCR 0x1243E054
133# define CONFIG_SYS_CLK 140000000
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500134#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135# define CONFIG_SYS_PLLCR 0x135a4140
136# define CONFIG_SYS_CLK 70000000
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500137#endif
138
139/*
140 * Low Level Configuration Settings
141 * (address mappings, register initial values, etc.)
142 * You should know what you are doing if you make changes here.
143 */
144
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
146#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500147
148/*
149 * Definitions for initial stack pointer and data area (in DPRAM)
150 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200152#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200153#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500155
156/*
157 * Start addresses for the final memory configuration
158 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500160 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_SDRAM_BASE 0x00000000
162#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500163
164#ifdef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165# define CONFIG_SYS_MONITOR_BASE 0x20000
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500166#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500168#endif
169
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_MONITOR_LEN 0x40000
171#define CONFIG_SYS_MALLOC_LEN (256 << 10)
172#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500173
174/*
175 * For booting Linux, the board info and command line data
176 * have to be in the first 8 MB of memory, since this is
177 * the maximum mapped by the Linux kernel during initialization ??
178 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChung Liewd6e4baf2009-01-27 12:57:47 +0000180#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500181
182/* FLASH organization */
TsiChung Liew012522f2008-10-21 10:03:07 +0000183#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
185#define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */
186#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500187
188#define FLASH_SST6401B 0x200
189#define SST_ID_xF6401B 0x236D236D
190
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#undef CONFIG_SYS_FLASH_CFI
192#ifdef CONFIG_SYS_FLASH_CFI
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500193/*
194 * Unable to use CFI driver, due to incompatible sector erase command by SST.
195 * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
196 * 0x30 is block erase in SST
197 */
Jean-Christophe PLAGNIOL-VILLARD0de0afb2008-08-15 18:32:41 +0200198# define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199# define CONFIG_SYS_FLASH_SIZE 0x800000
200# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500201# define CONFIG_FLASH_CFI_LEGACY
202#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203# define CONFIG_SYS_SST_SECT 2048
204# define CONFIG_SYS_SST_SECTSZ 0x1000
205# define CONFIG_SYS_FLASH_WRITE_TOUT 500
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500206#endif
207
208/* Cache Configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_CACHELINE_SIZE 16
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500210
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600211#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200212 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600213#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200214 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600215#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
216#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
217 CF_ADDRMASK(8) | \
218 CF_ACR_EN | CF_ACR_SM_ALL)
219#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
220 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
221 CF_ACR_EN | CF_ACR_SM_ALL)
222#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
223 CF_CACR_DBWE)
224
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500225/* Port configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_FECI2C 0xF0
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500227
TsiChung Liew012522f2008-10-21 10:03:07 +0000228#define CONFIG_SYS_CS0_BASE 0xFF800000
229#define CONFIG_SYS_CS0_MASK 0x007F0021
230#define CONFIG_SYS_CS0_CTRL 0x00001D80
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500231
TsiChung Liew012522f2008-10-21 10:03:07 +0000232#define CONFIG_SYS_CS1_BASE 0xE0000000
233#define CONFIG_SYS_CS1_MASK 0x00000001
234#define CONFIG_SYS_CS1_CTRL 0x00003DD8
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500235
236/*-----------------------------------------------------------------------
237 * Port configuration
238 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
240#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
241#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
242#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
243#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
244#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
245#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500246
247#endif /* _M5253DEMO_H */