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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +02002/*
3 * board.c
4 *
5 * Board functions for TCL SL50 board
6 *
7 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +02008 */
9
10#include <common.h>
Simon Glass4bfd1f52019-08-01 09:46:43 -060011#include <env.h>
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +020012#include <errno.h>
Simon Glass52559322019-11-14 12:57:46 -070013#include <init.h>
Simon Glass90526e92020-05-10 11:39:56 -060014#include <net.h>
Simon Glassb03e0512019-11-14 12:57:24 -070015#include <serial.h>
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +020016#include <spl.h>
17#include <asm/arch/cpu.h>
18#include <asm/arch/hardware.h>
19#include <asm/arch/omap.h>
20#include <asm/arch/ddr_defs.h>
21#include <asm/arch/clock.h>
22#include <asm/arch/gpio.h>
23#include <asm/arch/mmc_host_def.h>
24#include <asm/arch/sys_proto.h>
25#include <asm/arch/mem.h>
26#include <asm/io.h>
27#include <asm/emif.h>
28#include <asm/gpio.h>
29#include <i2c.h>
30#include <miiphy.h>
31#include <cpsw.h>
32#include <power/tps65217.h>
33#include <power/tps65910.h>
Simon Glassf3998fd2019-08-02 09:44:25 -060034#include <env_internal.h>
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +020035#include <watchdog.h>
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +020036#include "board.h"
37
38DECLARE_GLOBAL_DATA_PTR;
39
40static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
41
42#ifndef CONFIG_SKIP_LOWLEVEL_INIT
43
44static const struct ddr_data ddr3_sl50_data = {
45 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
46 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
47 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
48 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
49};
50
51static const struct cmd_control ddr3_sl50_cmd_ctrl_data = {
52 .cmd0csratio = MT41K256M16HA125E_RATIO,
53 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
54
55 .cmd1csratio = MT41K256M16HA125E_RATIO,
56 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
57
58 .cmd2csratio = MT41K256M16HA125E_RATIO,
59 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
60};
61
62static struct emif_regs ddr3_sl50_emif_reg_data = {
63 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
64 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
65 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
66 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
67 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
68 .zq_config = MT41K256M16HA125E_ZQ_CFG,
69 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
70};
71
72#ifdef CONFIG_SPL_OS_BOOT
73int spl_start_uboot(void)
74{
75 /* break into full u-boot on 'c' */
76 if (serial_tstc() && serial_getc() == 'c')
77 return 1;
78
79#ifdef CONFIG_SPL_ENV_SUPPORT
80 env_init();
Simon Glass310fb142017-08-03 12:22:07 -060081 env_load();
Simon Glassbfebc8c2017-08-03 12:22:13 -060082 if (env_get_yesno("boot_os") != 1)
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +020083 return 1;
84#endif
85
86 return 0;
87}
88#endif
89
90#define OSC (V_OSCK/1000000)
91const struct dpll_params dpll_ddr_sl50 = {
92 400, OSC-1, 1, -1, -1, -1, -1};
93
94void am33xx_spl_board_init(void)
95{
96 int mpu_vdd;
97
98 /* Get the frequency */
99 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
100
101 /* BeagleBone PMIC Code */
102 int usb_cur_lim;
103
104 if (i2c_probe(TPS65217_CHIP_PM))
105 return;
106
107 /*
108 * Increase USB current limit to 1300mA or 1800mA and set
109 * the MPU voltage controller as needed.
110 */
111 if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
112 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
113 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
114 } else {
115 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
116 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
117 }
118
119 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
120 TPS65217_POWER_PATH,
121 usb_cur_lim,
122 TPS65217_USB_INPUT_CUR_LIMIT_MASK))
123 puts("tps65217_reg_write failure\n");
124
125 /* Set DCDC3 (CORE) voltage to 1.125V */
126 if (tps65217_voltage_update(TPS65217_DEFDCDC3,
127 TPS65217_DCDC_VOLT_SEL_1125MV)) {
128 puts("tps65217_voltage_update failure\n");
129 return;
130 }
131
132 /* Set CORE Frequencies to OPP100 */
133 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
134
135 /* Set DCDC2 (MPU) voltage */
136 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
137 puts("tps65217_voltage_update failure\n");
138 return;
139 }
140
141 /*
142 * Set LDO3 to 1.8V and LDO4 to 3.3V
143 */
144 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
145 TPS65217_DEFLS1,
146 TPS65217_LDO_VOLTAGE_OUT_1_8,
147 TPS65217_LDO_MASK))
148 puts("tps65217_reg_write failure\n");
149
150 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
151 TPS65217_DEFLS2,
152 TPS65217_LDO_VOLTAGE_OUT_3_3,
153 TPS65217_LDO_MASK))
154 puts("tps65217_reg_write failure\n");
155
156 /* Set MPU Frequency to what we detected now that voltages are set */
157 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
158}
159
160const struct dpll_params *get_dpll_ddr_params(void)
161{
162 enable_i2c0_pin_mux();
163 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
164
165 return &dpll_ddr_sl50;
166}
167
168void set_uart_mux_conf(void)
169{
170#if CONFIG_CONS_INDEX == 1
171 enable_uart0_pin_mux();
172#elif CONFIG_CONS_INDEX == 2
173 enable_uart1_pin_mux();
174#elif CONFIG_CONS_INDEX == 3
175 enable_uart2_pin_mux();
176#elif CONFIG_CONS_INDEX == 4
177 enable_uart3_pin_mux();
178#elif CONFIG_CONS_INDEX == 5
179 enable_uart4_pin_mux();
180#elif CONFIG_CONS_INDEX == 6
181 enable_uart5_pin_mux();
182#endif
183}
184
185void set_mux_conf_regs(void)
186{
187 enable_board_pin_mux();
188}
189
190const struct ctrl_ioregs ioregs_evmsk = {
191 .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
192 .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
193 .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
194 .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
195 .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
196};
197
198const struct ctrl_ioregs ioregs_bonelt = {
199 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
200 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
201 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
202 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
203 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
204};
205
206const struct ctrl_ioregs ioregs_evm15 = {
207 .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
208 .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
209 .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
210 .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
211 .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
212};
213
214const struct ctrl_ioregs ioregs = {
215 .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
216 .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
217 .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
218 .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
219 .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
220};
221
222void sdram_init(void)
223{
224 config_ddr(400, &ioregs_bonelt,
225 &ddr3_sl50_data,
226 &ddr3_sl50_cmd_ctrl_data,
227 &ddr3_sl50_emif_reg_data, 0);
228}
229#endif
230
231/*
232 * Basic board specific setup. Pinmux has been handled already.
233 */
234int board_init(void)
235{
236#if defined(CONFIG_HW_WATCHDOG)
237 hw_watchdog_init();
238#endif
239
240 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
241 return 0;
242}
243
244#ifdef CONFIG_BOARD_LATE_INIT
245int board_late_init(void)
246{
247 return 0;
248}
249#endif
250
251#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
252 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
253static void cpsw_control(int enabled)
254{
255 /* VTP can be added here */
256
257 return;
258}
259
260static struct cpsw_slave_data cpsw_slaves[] = {
261 {
262 .slave_reg_ofs = 0x208,
263 .sliver_reg_ofs = 0xd80,
264 .phy_addr = 0,
265 },
266 {
267 .slave_reg_ofs = 0x308,
268 .sliver_reg_ofs = 0xdc0,
269 .phy_addr = 1,
270 },
271};
272
273static struct cpsw_platform_data cpsw_data = {
274 .mdio_base = CPSW_MDIO_BASE,
275 .cpsw_base = CPSW_BASE,
276 .mdio_div = 0xff,
277 .channels = 8,
278 .cpdma_reg_ofs = 0x800,
279 .slaves = 1,
280 .slave_data = cpsw_slaves,
281 .ale_reg_ofs = 0xd00,
282 .ale_entries = 1024,
283 .host_port_reg_ofs = 0x108,
284 .hw_stats_reg_ofs = 0x900,
285 .bd_ram_ofs = 0x2000,
286 .mac_control = (1 << 5),
287 .control = cpsw_control,
288 .host_port_num = 0,
289 .version = CPSW_CTRL_VERSION_2,
290};
291#endif
292
293/*
294 * This function will:
295 * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
296 * in the environment
297 * Perform fixups to the PHY present on certain boards. We only need this
298 * function in:
299 * - SPL with either CPSW or USB ethernet support
300 * - Full U-Boot, with either CPSW or USB ethernet
301 * Build in only these cases to avoid warnings about unused variables
302 * when we build an SPL that has neither option but full U-Boot will.
303 */
Faiz Abbasb432b1e2018-02-16 21:17:44 +0530304#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) \
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +0200305 && defined(CONFIG_SPL_BUILD)) || \
306 ((defined(CONFIG_DRIVER_TI_CPSW) || \
307 defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
308 !defined(CONFIG_SPL_BUILD))
309int board_eth_init(bd_t *bis)
310{
311 int rv, n = 0;
312 uint8_t mac_addr[6];
313 uint32_t mac_hi, mac_lo;
314
315 /* try reading mac address from efuse */
316 mac_lo = readl(&cdev->macid0l);
317 mac_hi = readl(&cdev->macid0h);
318 mac_addr[0] = mac_hi & 0xFF;
319 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
320 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
321 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
322 mac_addr[4] = mac_lo & 0xFF;
323 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
324
325#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
326 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
Simon Glass00caae62017-08-03 12:22:12 -0600327 if (!env_get("ethaddr")) {
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +0200328 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
329
330 if (is_valid_ethaddr(mac_addr))
Simon Glassfd1e9592017-08-03 12:22:11 -0600331 eth_env_set_enetaddr("ethaddr", mac_addr);
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +0200332 }
333
334#ifdef CONFIG_DRIVER_TI_CPSW
335
336 mac_lo = readl(&cdev->macid1l);
337 mac_hi = readl(&cdev->macid1h);
338 mac_addr[0] = mac_hi & 0xFF;
339 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
340 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
341 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
342 mac_addr[4] = mac_lo & 0xFF;
343 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
344
Simon Glass00caae62017-08-03 12:22:12 -0600345 if (!env_get("eth1addr")) {
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +0200346 if (is_valid_ethaddr(mac_addr))
Simon Glassfd1e9592017-08-03 12:22:11 -0600347 eth_env_set_enetaddr("eth1addr", mac_addr);
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +0200348 }
349
350
351 writel(MII_MODE_ENABLE, &cdev->miisel);
352 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
353 PHY_INTERFACE_MODE_MII;
354
355 rv = cpsw_register(&cpsw_data);
356 if (rv < 0)
357 printf("Error %d registering CPSW switch\n", rv);
358 else
359 n += rv;
360#endif
361
362 /*
363 *
364 * CPSW RGMII Internal Delay Mode is not supported in all PVT
365 * operating points. So we must set the TX clock delay feature
366 * in the AR8051 PHY. Since we only support a single ethernet
367 * device in U-Boot, we only do this for the first instance.
368 */
369#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
370#define AR8051_PHY_DEBUG_DATA_REG 0x1e
371#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
372#define AR8051_RGMII_TX_CLK_DLY 0x100
373
374#endif
375#if defined(CONFIG_USB_ETHER) && \
Faiz Abbasb432b1e2018-02-16 21:17:44 +0530376 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +0200377 if (is_valid_ether_addr(mac_addr))
Simon Glassfd1e9592017-08-03 12:22:11 -0600378 eth_env_set_enetaddr("usbnet_devaddr", mac_addr);
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +0200379
380 rv = usb_eth_initialize(bis);
381 if (rv < 0)
382 printf("Error %d registering USB_ETHER\n", rv);
383 else
384 n += rv;
385#endif
386 return n;
387}
388#endif