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wdenkf8cac652002-08-26 22:36:39 +00001/*
2 * (C) Copyright 2001
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2001-2002
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <malloc.h>
29#include <mpc8xx.h>
30
Wolfgang Denkd87080b2006-03-31 18:32:53 +020031DECLARE_GLOBAL_DATA_PTR;
wdenkf8cac652002-08-26 22:36:39 +000032
33static long int dram_size (long int, long int *, long int);
34
wdenkf8cac652002-08-26 22:36:39 +000035#define _NOT_USED_ 0xFFFFFFFF
36
wdenkc83bf6a2004-01-06 22:38:14 +000037const uint sdram_table[] = {
wdenkf8cac652002-08-26 22:36:39 +000038#if (MPC8XX_SPEED <= 50000000L)
39 /*
40 * Single Read. (Offset 0 in UPMA RAM)
41 */
wdenkc83bf6a2004-01-06 22:38:14 +000042 0x0F07EC04, 0x01BBD804, 0x1FF7F440, 0xFFFFFC07,
wdenkf8cac652002-08-26 22:36:39 +000043 0xFFFFFFFF,
44
45 /*
46 * SDRAM Initialization (offset 5 in UPMA RAM)
47 *
48 * This is no UPM entry point. The following definition uses
49 * the remaining space to establish an initialization
50 * sequence, which is executed by a RUN command.
51 *
52 */
wdenkc83bf6a2004-01-06 22:38:14 +000053 0x1FE7F434, 0xEFABE834, 0x1FA7D435,
wdenkf8cac652002-08-26 22:36:39 +000054
55 /*
56 * Burst Read. (Offset 8 in UPMA RAM)
57 */
wdenkc83bf6a2004-01-06 22:38:14 +000058 0x0F07EC04, 0x10EFDC04, 0xF0AFFC00, 0xF0AFFC00,
59 0xF1AFFC00, 0xFFAFFC40, 0xFFAFFC07, 0xFFFFFFFF,
60 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
61 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
wdenkf8cac652002-08-26 22:36:39 +000062
63 /*
64 * Single Write. (Offset 18 in UPMA RAM)
65 */
wdenkc83bf6a2004-01-06 22:38:14 +000066 0x0E07E804, 0x01BBD000, 0x1FF7F447, 0xFFFFFFFF,
67 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
wdenkf8cac652002-08-26 22:36:39 +000068
69 /*
70 * Burst Write. (Offset 20 in UPMA RAM)
71 */
wdenkc83bf6a2004-01-06 22:38:14 +000072 0x0E07E800, 0x10EFD400, 0xF0AFFC00, 0xF0AFFC00,
73 0xF1AFFC47, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
74 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
75 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
wdenkf8cac652002-08-26 22:36:39 +000076
77 /*
78 * Refresh (Offset 30 in UPMA RAM)
79 */
wdenkc83bf6a2004-01-06 22:38:14 +000080 0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC84, 0xFFFFFC07,
81 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
82 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
wdenkf8cac652002-08-26 22:36:39 +000083
84 /*
85 * Exception. (Offset 3c in UPMA RAM)
86 */
wdenkc83bf6a2004-01-06 22:38:14 +000087 0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF
wdenkf8cac652002-08-26 22:36:39 +000088#else
89
90 /*
91 * Single Read. (Offset 0 in UPMA RAM)
92 */
wdenkc83bf6a2004-01-06 22:38:14 +000093 0x1F07FC04, 0xEEAFEC04, 0x11AFDC04, 0xEFBBF800,
wdenkf8cac652002-08-26 22:36:39 +000094 0x1FF7F447,
95
96 /*
97 * SDRAM Initialization (offset 5 in UPMA RAM)
98 *
99 * This is no UPM entry point. The following definition uses
100 * the remaining space to establish an initialization
101 * sequence, which is executed by a RUN command.
102 *
103 */
wdenkc83bf6a2004-01-06 22:38:14 +0000104 0x1FF7F434, 0xEFEBE834, 0x1FB7D435,
wdenkf8cac652002-08-26 22:36:39 +0000105
106 /*
107 * Burst Read. (Offset 8 in UPMA RAM)
108 */
wdenkc83bf6a2004-01-06 22:38:14 +0000109 0x1F07FC04, 0xEEAFEC04, 0x10AFDC04, 0xF0AFFC00,
110 0xF0AFFC00, 0xF1AFFC00, 0xEFBBF800, 0x1FF7F447,
wdenkf8cac652002-08-26 22:36:39 +0000111 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
112 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
113
114 /*
115 * Single Write. (Offset 18 in UPMA RAM)
116 */
wdenkc83bf6a2004-01-06 22:38:14 +0000117 0x1F07FC04, 0xEEAFE800, 0x01BBD004, 0x1FF7F447,
wdenkf8cac652002-08-26 22:36:39 +0000118 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
119
120 /*
121 * Burst Write. (Offset 20 in UPMA RAM)
122 */
wdenkc83bf6a2004-01-06 22:38:14 +0000123 0x1F07FC04, 0xEEAFE800, 0x10AFD400, 0xF0AFFC00,
124 0xF0AFFC00, 0xE1BBF804, 0x1FF7F447, _NOT_USED_,
125 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
wdenkf8cac652002-08-26 22:36:39 +0000126 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
127
128 /*
129 * Refresh (Offset 30 in UPMA RAM)
130 */
wdenkc83bf6a2004-01-06 22:38:14 +0000131 0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
132 0xFFFFFC84, 0xFFFFFC07,
wdenkf8cac652002-08-26 22:36:39 +0000133 _NOT_USED_, _NOT_USED_, _NOT_USED_,
134 _NOT_USED_, _NOT_USED_, _NOT_USED_,
135
136 /*
137 * Exception. (Offset 3c in UPMA RAM)
138 */
139 0x7FFFFC07, /* last */
wdenkc83bf6a2004-01-06 22:38:14 +0000140 _NOT_USED_, _NOT_USED_, _NOT_USED_,
wdenkf8cac652002-08-26 22:36:39 +0000141#endif
142};
143
144/* ------------------------------------------------------------------------- */
145
146
147/*
148 * Check Board Identity:
149 *
150 */
151
152int checkboard (void)
153{
wdenkc83bf6a2004-01-06 22:38:14 +0000154 printf ("Board: Nexus NX823");
155 return (0);
wdenkf8cac652002-08-26 22:36:39 +0000156}
157
158/* ------------------------------------------------------------------------- */
159
Becky Bruce9973e3c2008-06-09 16:03:40 -0500160phys_size_t initdram (int board_type)
wdenkf8cac652002-08-26 22:36:39 +0000161{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkc83bf6a2004-01-06 22:38:14 +0000163 volatile memctl8xx_t *memctl = &immap->im_memctl;
164 long int size_b0, size_b1, size8, size9;
wdenkf8cac652002-08-26 22:36:39 +0000165
wdenkc83bf6a2004-01-06 22:38:14 +0000166 upmconfig (UPMA, (uint *) sdram_table,
167 sizeof (sdram_table) / sizeof (uint));
wdenkf8cac652002-08-26 22:36:39 +0000168
wdenkc83bf6a2004-01-06 22:38:14 +0000169 /*
170 * Up to 2 Banks of 64Mbit x 2 devices
171 * Initial builds only have 1
172 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173 memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K;
wdenkc83bf6a2004-01-06 22:38:14 +0000174 memctl->memc_mar = 0x00000088;
wdenkf8cac652002-08-26 22:36:39 +0000175
wdenkc83bf6a2004-01-06 22:38:14 +0000176 /*
177 * Map controller SDRAM bank 0
178 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179 memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
180 memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
181 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
wdenkc83bf6a2004-01-06 22:38:14 +0000182 udelay (200);
wdenkf8cac652002-08-26 22:36:39 +0000183
wdenkc83bf6a2004-01-06 22:38:14 +0000184 /*
185 * Map controller SDRAM bank 1
186 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187 memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
188 memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
wdenkf8cac652002-08-26 22:36:39 +0000189
wdenkc83bf6a2004-01-06 22:38:14 +0000190 /*
191 * Perform SDRAM initializsation sequence
192 */
193 memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
194 udelay (1);
195 memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */
196 udelay (1);
wdenkf8cac652002-08-26 22:36:39 +0000197
wdenkc83bf6a2004-01-06 22:38:14 +0000198 memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */
199 udelay (1);
200 memctl->memc_mcr = 0x80004230; /* SDRAM bank 1 - execute twice */
201 udelay (1);
wdenkf8cac652002-08-26 22:36:39 +0000202
wdenkc83bf6a2004-01-06 22:38:14 +0000203 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
204 udelay (1000);
wdenkf8cac652002-08-26 22:36:39 +0000205
wdenkc83bf6a2004-01-06 22:38:14 +0000206 /*
207 * Preliminary prescaler for refresh (depends on number of
208 * banks): This value is selected for four cycles every 62.4 us
209 * with two SDRAM banks or four cycles every 31.2 us with one
210 * bank. It will be adjusted after memory sizing.
211 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212 memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
wdenkf8cac652002-08-26 22:36:39 +0000213
wdenkc83bf6a2004-01-06 22:38:14 +0000214 memctl->memc_mar = 0x00000088;
wdenkf8cac652002-08-26 22:36:39 +0000215
216
wdenkc83bf6a2004-01-06 22:38:14 +0000217 /*
218 * Check Bank 0 Memory Size for re-configuration
219 *
220 * try 8 column mode
221 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222 size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE1_PRELIM,
wdenkc83bf6a2004-01-06 22:38:14 +0000223 SDRAM_MAX_SIZE);
wdenkf8cac652002-08-26 22:36:39 +0000224
wdenkc83bf6a2004-01-06 22:38:14 +0000225 udelay (1000);
wdenkf8cac652002-08-26 22:36:39 +0000226
wdenkc83bf6a2004-01-06 22:38:14 +0000227 /*
228 * try 9 column mode
229 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230 size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE1_PRELIM,
wdenkc83bf6a2004-01-06 22:38:14 +0000231 SDRAM_MAX_SIZE);
wdenkf8cac652002-08-26 22:36:39 +0000232
wdenkc83bf6a2004-01-06 22:38:14 +0000233 if (size8 < size9) { /* leave configuration at 9 columns */
234 size_b0 = size9;
wdenkf8cac652002-08-26 22:36:39 +0000235/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
wdenkc83bf6a2004-01-06 22:38:14 +0000236 } else { /* back to 8 columns */
237 size_b0 = size8;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
wdenkc83bf6a2004-01-06 22:38:14 +0000239 udelay (500);
wdenkf8cac652002-08-26 22:36:39 +0000240/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
wdenkc83bf6a2004-01-06 22:38:14 +0000241 }
wdenkf8cac652002-08-26 22:36:39 +0000242
243 /*
244 * Check Bank 1 Memory Size
245 * use current column settings
246 * [9 column SDRAM may also be used in 8 column mode,
247 * but then only half the real size will be used.]
248 */
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200249 size_b1 = dram_size (memctl->memc_mamr, (long *) SDRAM_BASE2_PRELIM,
wdenkc83bf6a2004-01-06 22:38:14 +0000250 SDRAM_MAX_SIZE);
wdenkf8cac652002-08-26 22:36:39 +0000251/* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */
252
wdenkc83bf6a2004-01-06 22:38:14 +0000253 udelay (1000);
wdenkf8cac652002-08-26 22:36:39 +0000254
wdenkc83bf6a2004-01-06 22:38:14 +0000255 /*
256 * Adjust refresh rate depending on SDRAM type, both banks
257 * For types > 128 MBit leave it at the current (fast) rate
258 */
259 if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
260 /* reduce to 15.6 us (62.4 us / quad) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261 memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
wdenkc83bf6a2004-01-06 22:38:14 +0000262 udelay (1000);
wdenkf8cac652002-08-26 22:36:39 +0000263 }
264
wdenkc83bf6a2004-01-06 22:38:14 +0000265 /*
266 * Final mapping: map bigger bank first
267 */
268 if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
wdenkf8cac652002-08-26 22:36:39 +0000269
wdenkc83bf6a2004-01-06 22:38:14 +0000270 memctl->memc_or2 =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271 ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
wdenkc83bf6a2004-01-06 22:38:14 +0000272 memctl->memc_br2 =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273 (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
wdenkf8cac652002-08-26 22:36:39 +0000274
wdenkc83bf6a2004-01-06 22:38:14 +0000275 if (size_b0 > 0) {
276 /*
277 * Position Bank 0 immediately above Bank 1
278 */
279 memctl->memc_or1 =
280 ((-size_b0) & 0xFFFF0000) |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281 CONFIG_SYS_OR_TIMING_SDRAM;
wdenkc83bf6a2004-01-06 22:38:14 +0000282 memctl->memc_br1 =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283 ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
wdenkc83bf6a2004-01-06 22:38:14 +0000284 BR_V)
285 + size_b1;
286 } else {
287 unsigned long reg;
wdenkf8cac652002-08-26 22:36:39 +0000288
wdenkc83bf6a2004-01-06 22:38:14 +0000289 /*
290 * No bank 0
291 *
292 * invalidate bank
293 */
294 memctl->memc_br1 = 0;
295
296 /* adjust refresh rate depending on SDRAM type, one bank */
297 reg = memctl->memc_mptpr;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298 reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
wdenkc83bf6a2004-01-06 22:38:14 +0000299 memctl->memc_mptpr = reg;
300 }
301
302 } else { /* SDRAM Bank 0 is bigger - map first */
303
304 memctl->memc_or1 =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305 ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
wdenkc83bf6a2004-01-06 22:38:14 +0000306 memctl->memc_br1 =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307 (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
wdenkc83bf6a2004-01-06 22:38:14 +0000308
309 if (size_b1 > 0) {
310 /*
311 * Position Bank 1 immediately above Bank 0
312 */
313 memctl->memc_or2 =
314 ((-size_b1) & 0xFFFF0000) |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315 CONFIG_SYS_OR_TIMING_SDRAM;
wdenkc83bf6a2004-01-06 22:38:14 +0000316 memctl->memc_br2 =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317 ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
wdenkc83bf6a2004-01-06 22:38:14 +0000318 BR_V)
319 + size_b0;
320 } else {
321 unsigned long reg;
322
323 /*
324 * No bank 1
325 *
326 * invalidate bank
327 */
328 memctl->memc_br2 = 0;
329
330 /* adjust refresh rate depending on SDRAM type, one bank */
331 reg = memctl->memc_mptpr;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332 reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
wdenkc83bf6a2004-01-06 22:38:14 +0000333 memctl->memc_mptpr = reg;
334 }
wdenkf8cac652002-08-26 22:36:39 +0000335 }
wdenkf8cac652002-08-26 22:36:39 +0000336
wdenkc83bf6a2004-01-06 22:38:14 +0000337 udelay (10000);
wdenkf8cac652002-08-26 22:36:39 +0000338
wdenkc83bf6a2004-01-06 22:38:14 +0000339 return (size_b0 + size_b1);
wdenkf8cac652002-08-26 22:36:39 +0000340}
341
342/* ------------------------------------------------------------------------- */
343
344/*
345 * Check memory range for valid RAM. A simple memory test determines
346 * the actually available RAM size between addresses `base' and
347 * `base + maxsize'. Some (not all) hardware errors are detected:
348 * - short between address lines
349 * - short between data lines
350 */
351
wdenkc83bf6a2004-01-06 22:38:14 +0000352static long int dram_size (long int mamr_value, long int *base,
353 long int maxsize)
wdenkf8cac652002-08-26 22:36:39 +0000354{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkc83bf6a2004-01-06 22:38:14 +0000356 volatile memctl8xx_t *memctl = &immap->im_memctl;
wdenkf8cac652002-08-26 22:36:39 +0000357
wdenkc83bf6a2004-01-06 22:38:14 +0000358 memctl->memc_mamr = mamr_value;
wdenkf8cac652002-08-26 22:36:39 +0000359
wdenkc83bf6a2004-01-06 22:38:14 +0000360 return (get_ram_size (base, maxsize));
wdenkf8cac652002-08-26 22:36:39 +0000361}
362
wdenkf8cac652002-08-26 22:36:39 +0000363int misc_init_r (void)
364{
Mike Frysinger0107cf62009-02-11 19:36:20 -0500365 int i;
wdenkf8cac652002-08-26 22:36:39 +0000366 char tmp[50];
Mike Frysinger0107cf62009-02-11 19:36:20 -0500367 uchar ethaddr[6];
368 bd_t *bd = gd->bd;
369 ulong my_sernum = bd->bi_sernum;
wdenkf8cac652002-08-26 22:36:39 +0000370
Mike Frysinger0107cf62009-02-11 19:36:20 -0500371 /* load unique serial number */
372 for (i = 0; i < 8; ++i)
373 bd->bi_sernum[i] = *(u_char *) (CONFIG_SYS_FLASH_SN_BASE + i);
wdenkf8cac652002-08-26 22:36:39 +0000374
375 /* save env variables according to sernum */
wdenkc83bf6a2004-01-06 22:38:14 +0000376 sprintf (tmp, "%08lx%08lx", my_sernum[0], my_sernum[1]);
377 setenv ("serial#", tmp);
wdenkf8cac652002-08-26 22:36:39 +0000378
Mike Frysinger0107cf62009-02-11 19:36:20 -0500379 if (!eth_getenv_enetaddr("ethaddr", ethaddr)) {
380 ethaddr[0] = 0x10;
381 ethaddr[1] = 0x20;
382 ethaddr[2] = 0x30;
383 ethaddr[3] = bd->bi_sernum[1] << 4 | bd->bi_sernum[2];
384 ethaddr[4] = bd->bi_sernum[5];
385 ethaddr[5] = bd->bi_sernum[6];
wdenkf8cac652002-08-26 22:36:39 +0000386 }
Mike Frysinger0107cf62009-02-11 19:36:20 -0500387
388 return 0;
wdenkf8cac652002-08-26 22:36:39 +0000389}