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wdenk3d3befa2004-03-14 15:06:13 +00001/*
2 * (C) Copyright 2000
3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
4 *
5 * (C) Copyright 2004
6 * ARM Ltd.
7 * Philippe Robin, <philippe.robin@arm.com>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
Andreas Engel48d01922008-09-08 14:30:53 +020028/* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
wdenk3d3befa2004-03-14 15:06:13 +000029
30#include <common.h>
Stuart Wood8b616ed2008-06-02 16:42:19 -040031#include <watchdog.h>
Matt Waddel249d5212010-10-07 15:48:46 -060032#include <asm/io.h>
Marek Vasut39f61472012-09-14 22:38:46 +020033#include <serial.h>
34#include <linux/compiler.h>
Andreas Engel20c92262008-09-08 10:17:31 +020035#include "serial_pl01x.h"
wdenk3d3befa2004-03-14 15:06:13 +000036
Andreas Engel20c92262008-09-08 10:17:31 +020037/*
38 * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
39 * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
40 * Versatile PB has four UARTs.
41 */
wdenk3d3befa2004-03-14 15:06:13 +000042#define CONSOLE_PORT CONFIG_CONS_INDEX
wdenk6705d812004-08-02 23:22:59 +000043static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
44#define NUM_PORTS (sizeof(port)/sizeof(port[0]))
wdenk3d3befa2004-03-14 15:06:13 +000045
Andreas Engel20c92262008-09-08 10:17:31 +020046static void pl01x_putc (int portnum, char c);
47static int pl01x_getc (int portnum);
48static int pl01x_tstc (int portnum);
Matt Waddel249d5212010-10-07 15:48:46 -060049unsigned int baudrate = CONFIG_BAUDRATE;
50DECLARE_GLOBAL_DATA_PTR;
wdenk3d3befa2004-03-14 15:06:13 +000051
Rabin Vincent72d5e442010-05-05 09:23:07 +053052static struct pl01x_regs *pl01x_get_regs(int portnum)
53{
54 return (struct pl01x_regs *) port[portnum];
55}
56
Andreas Engel48d01922008-09-08 14:30:53 +020057#ifdef CONFIG_PL010_SERIAL
wdenk3d3befa2004-03-14 15:06:13 +000058
Marek Vasut39f61472012-09-14 22:38:46 +020059static int pl01x_serial_init(void)
wdenk3d3befa2004-03-14 15:06:13 +000060{
Rabin Vincent72d5e442010-05-05 09:23:07 +053061 struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
wdenk42dfe7a2004-03-14 22:25:36 +000062 unsigned int divisor;
wdenk3d3befa2004-03-14 15:06:13 +000063
Matt Waddel249d5212010-10-07 15:48:46 -060064 /* First, disable everything */
Rabin Vincent72d5e442010-05-05 09:23:07 +053065 writel(0, &regs->pl010_cr);
wdenk3d3befa2004-03-14 15:06:13 +000066
Matt Waddel249d5212010-10-07 15:48:46 -060067 /* Set baud rate */
68 switch (baudrate) {
wdenk42dfe7a2004-03-14 22:25:36 +000069 case 9600:
70 divisor = UART_PL010_BAUD_9600;
71 break;
wdenk3d3befa2004-03-14 15:06:13 +000072
wdenk42dfe7a2004-03-14 22:25:36 +000073 case 19200:
74 divisor = UART_PL010_BAUD_9600;
75 break;
wdenk3d3befa2004-03-14 15:06:13 +000076
wdenk42dfe7a2004-03-14 22:25:36 +000077 case 38400:
78 divisor = UART_PL010_BAUD_38400;
79 break;
wdenk3d3befa2004-03-14 15:06:13 +000080
wdenk42dfe7a2004-03-14 22:25:36 +000081 case 57600:
82 divisor = UART_PL010_BAUD_57600;
83 break;
wdenk3d3befa2004-03-14 15:06:13 +000084
wdenk42dfe7a2004-03-14 22:25:36 +000085 case 115200:
86 divisor = UART_PL010_BAUD_115200;
87 break;
wdenk3d3befa2004-03-14 15:06:13 +000088
wdenk42dfe7a2004-03-14 22:25:36 +000089 default:
90 divisor = UART_PL010_BAUD_38400;
91 }
wdenk3d3befa2004-03-14 15:06:13 +000092
Rabin Vincent72d5e442010-05-05 09:23:07 +053093 writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm);
94 writel(divisor & 0xff, &regs->pl010_lcrl);
wdenk3d3befa2004-03-14 15:06:13 +000095
Matt Waddel249d5212010-10-07 15:48:46 -060096 /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
Rabin Vincent72d5e442010-05-05 09:23:07 +053097 writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN, &regs->pl010_lcrh);
wdenk3d3befa2004-03-14 15:06:13 +000098
Matt Waddel249d5212010-10-07 15:48:46 -060099 /* Finally, enable the UART */
Rabin Vincent72d5e442010-05-05 09:23:07 +0530100 writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);
wdenk42dfe7a2004-03-14 22:25:36 +0000101
Andreas Engel20c92262008-09-08 10:17:31 +0200102 return 0;
wdenk3d3befa2004-03-14 15:06:13 +0000103}
104
Andreas Engel48d01922008-09-08 14:30:53 +0200105#endif /* CONFIG_PL010_SERIAL */
Andreas Engel20c92262008-09-08 10:17:31 +0200106
Andreas Engel48d01922008-09-08 14:30:53 +0200107#ifdef CONFIG_PL011_SERIAL
Andreas Engel20c92262008-09-08 10:17:31 +0200108
Marek Vasut39f61472012-09-14 22:38:46 +0200109static int pl01x_serial_init(void)
Andreas Engel20c92262008-09-08 10:17:31 +0200110{
Rabin Vincent72d5e442010-05-05 09:23:07 +0530111 struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
Andreas Engel20c92262008-09-08 10:17:31 +0200112 unsigned int temp;
113 unsigned int divider;
114 unsigned int remainder;
115 unsigned int fraction;
John Rigby910f1ae2011-04-19 10:42:39 +0000116 unsigned int lcr;
117
118#ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
119 /* Empty RX fifo if necessary */
120 if (readl(&regs->pl011_cr) & UART_PL011_CR_UARTEN) {
121 while (!(readl(&regs->fr) & UART_PL01x_FR_RXFE))
122 readl(&regs->dr);
123 }
124#endif
Andreas Engel20c92262008-09-08 10:17:31 +0200125
Matt Waddel249d5212010-10-07 15:48:46 -0600126 /* First, disable everything */
Rabin Vincent72d5e442010-05-05 09:23:07 +0530127 writel(0, &regs->pl011_cr);
Andreas Engel20c92262008-09-08 10:17:31 +0200128
129 /*
Matt Waddel249d5212010-10-07 15:48:46 -0600130 * Set baud rate
131 *
132 * IBRD = UART_CLK / (16 * BAUD_RATE)
133 * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE))
Andreas Engel20c92262008-09-08 10:17:31 +0200134 */
Matt Waddel249d5212010-10-07 15:48:46 -0600135 temp = 16 * baudrate;
Andreas Engel20c92262008-09-08 10:17:31 +0200136 divider = CONFIG_PL011_CLOCK / temp;
137 remainder = CONFIG_PL011_CLOCK % temp;
Matt Waddel249d5212010-10-07 15:48:46 -0600138 temp = (8 * remainder) / baudrate;
Andreas Engel20c92262008-09-08 10:17:31 +0200139 fraction = (temp >> 1) + (temp & 1);
140
Rabin Vincent72d5e442010-05-05 09:23:07 +0530141 writel(divider, &regs->pl011_ibrd);
142 writel(fraction, &regs->pl011_fbrd);
Andreas Engel20c92262008-09-08 10:17:31 +0200143
Matt Waddel249d5212010-10-07 15:48:46 -0600144 /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
John Rigby910f1ae2011-04-19 10:42:39 +0000145 lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
146 writel(lcr, &regs->pl011_lcrh);
Andreas Engel20c92262008-09-08 10:17:31 +0200147
John Rigby910f1ae2011-04-19 10:42:39 +0000148#ifdef CONFIG_PL011_SERIAL_RLCR
149 {
150 int i;
151
152 /*
153 * Program receive line control register after waiting
154 * 10 bus cycles. Delay be writing to readonly register
155 * 10 times
156 */
157 for (i = 0; i < 10; i++)
158 writel(lcr, &regs->fr);
159
160 writel(lcr, &regs->pl011_rlcr);
Mathieu J. Poirier84dee302012-08-03 11:05:12 +0000161 /* lcrh needs to be set again for change to be effective */
162 writel(lcr, &regs->pl011_lcrh);
John Rigby910f1ae2011-04-19 10:42:39 +0000163 }
164#endif
Matt Waddel249d5212010-10-07 15:48:46 -0600165 /* Finally, enable the UART */
Joshua Housh10501df2012-12-02 17:09:26 +0000166 writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE |
167 UART_PL011_CR_RTS, &regs->pl011_cr);
Andreas Engel20c92262008-09-08 10:17:31 +0200168
169 return 0;
170}
171
Andreas Engel48d01922008-09-08 14:30:53 +0200172#endif /* CONFIG_PL011_SERIAL */
Andreas Engel20c92262008-09-08 10:17:31 +0200173
Marek Vasut39f61472012-09-14 22:38:46 +0200174static void pl01x_serial_putc(const char c)
wdenk3d3befa2004-03-14 15:06:13 +0000175{
176 if (c == '\n')
Andreas Engel20c92262008-09-08 10:17:31 +0200177 pl01x_putc (CONSOLE_PORT, '\r');
wdenk3d3befa2004-03-14 15:06:13 +0000178
Andreas Engel20c92262008-09-08 10:17:31 +0200179 pl01x_putc (CONSOLE_PORT, c);
wdenk3d3befa2004-03-14 15:06:13 +0000180}
181
Marek Vasut39f61472012-09-14 22:38:46 +0200182static int pl01x_serial_getc(void)
wdenk3d3befa2004-03-14 15:06:13 +0000183{
Andreas Engel20c92262008-09-08 10:17:31 +0200184 return pl01x_getc (CONSOLE_PORT);
wdenk3d3befa2004-03-14 15:06:13 +0000185}
186
Marek Vasut39f61472012-09-14 22:38:46 +0200187static int pl01x_serial_tstc(void)
wdenk3d3befa2004-03-14 15:06:13 +0000188{
Andreas Engel20c92262008-09-08 10:17:31 +0200189 return pl01x_tstc (CONSOLE_PORT);
wdenk3d3befa2004-03-14 15:06:13 +0000190}
191
Marek Vasut39f61472012-09-14 22:38:46 +0200192static void pl01x_serial_setbrg(void)
wdenk3d3befa2004-03-14 15:06:13 +0000193{
Linus Walleij96baa4c2011-10-02 11:52:52 +0000194 struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
195
Matt Waddel249d5212010-10-07 15:48:46 -0600196 baudrate = gd->baudrate;
Linus Walleij96baa4c2011-10-02 11:52:52 +0000197 /*
198 * Flush FIFO and wait for non-busy before changing baudrate to avoid
199 * crap in console
200 */
201 while (!(readl(&regs->fr) & UART_PL01x_FR_TXFE))
202 WATCHDOG_RESET();
203 while (readl(&regs->fr) & UART_PL01x_FR_BUSY)
204 WATCHDOG_RESET();
Matt Waddel249d5212010-10-07 15:48:46 -0600205 serial_init();
wdenk3d3befa2004-03-14 15:06:13 +0000206}
207
Andreas Engel20c92262008-09-08 10:17:31 +0200208static void pl01x_putc (int portnum, char c)
wdenk3d3befa2004-03-14 15:06:13 +0000209{
Rabin Vincent72d5e442010-05-05 09:23:07 +0530210 struct pl01x_regs *regs = pl01x_get_regs(portnum);
211
wdenk42dfe7a2004-03-14 22:25:36 +0000212 /* Wait until there is space in the FIFO */
Rabin Vincent72d5e442010-05-05 09:23:07 +0530213 while (readl(&regs->fr) & UART_PL01x_FR_TXFF)
Stuart Wood8b616ed2008-06-02 16:42:19 -0400214 WATCHDOG_RESET();
wdenk42dfe7a2004-03-14 22:25:36 +0000215
216 /* Send the character */
Rabin Vincent72d5e442010-05-05 09:23:07 +0530217 writel(c, &regs->dr);
wdenk3d3befa2004-03-14 15:06:13 +0000218}
219
Andreas Engel20c92262008-09-08 10:17:31 +0200220static int pl01x_getc (int portnum)
wdenk3d3befa2004-03-14 15:06:13 +0000221{
Rabin Vincent72d5e442010-05-05 09:23:07 +0530222 struct pl01x_regs *regs = pl01x_get_regs(portnum);
wdenk42dfe7a2004-03-14 22:25:36 +0000223 unsigned int data;
wdenk3d3befa2004-03-14 15:06:13 +0000224
wdenk42dfe7a2004-03-14 22:25:36 +0000225 /* Wait until there is data in the FIFO */
Rabin Vincent72d5e442010-05-05 09:23:07 +0530226 while (readl(&regs->fr) & UART_PL01x_FR_RXFE)
Stuart Wood8b616ed2008-06-02 16:42:19 -0400227 WATCHDOG_RESET();
wdenk42dfe7a2004-03-14 22:25:36 +0000228
Rabin Vincent72d5e442010-05-05 09:23:07 +0530229 data = readl(&regs->dr);
wdenk42dfe7a2004-03-14 22:25:36 +0000230
231 /* Check for an error flag */
232 if (data & 0xFFFFFF00) {
233 /* Clear the error */
Rabin Vincent72d5e442010-05-05 09:23:07 +0530234 writel(0xFFFFFFFF, &regs->ecr);
wdenk42dfe7a2004-03-14 22:25:36 +0000235 return -1;
236 }
237
238 return (int) data;
wdenk3d3befa2004-03-14 15:06:13 +0000239}
240
Andreas Engel20c92262008-09-08 10:17:31 +0200241static int pl01x_tstc (int portnum)
wdenk3d3befa2004-03-14 15:06:13 +0000242{
Rabin Vincent72d5e442010-05-05 09:23:07 +0530243 struct pl01x_regs *regs = pl01x_get_regs(portnum);
244
Stuart Wood8b616ed2008-06-02 16:42:19 -0400245 WATCHDOG_RESET();
Rabin Vincent72d5e442010-05-05 09:23:07 +0530246 return !(readl(&regs->fr) & UART_PL01x_FR_RXFE);
wdenk3d3befa2004-03-14 15:06:13 +0000247}
Marek Vasut39f61472012-09-14 22:38:46 +0200248
Marek Vasut39f61472012-09-14 22:38:46 +0200249static struct serial_device pl01x_serial_drv = {
250 .name = "pl01x_serial",
251 .start = pl01x_serial_init,
252 .stop = NULL,
253 .setbrg = pl01x_serial_setbrg,
254 .putc = pl01x_serial_putc,
Marek Vasutec3fd682012-10-06 14:07:02 +0000255 .puts = default_serial_puts,
Marek Vasut39f61472012-09-14 22:38:46 +0200256 .getc = pl01x_serial_getc,
257 .tstc = pl01x_serial_tstc,
258};
259
260void pl01x_serial_initialize(void)
261{
262 serial_register(&pl01x_serial_drv);
263}
264
265__weak struct serial_device *default_serial_console(void)
266{
267 return &pl01x_serial_drv;
268}