| commit | fc4e69f63f96d6f8898864f1a9f9b0a4c0ac426b | [log] [tgz] |
|---|---|---|
| author | Fabio Estevam <festevam@gmail.com> | Wed Oct 07 08:09:32 2020 -0300 |
| committer | Stefano Babic <sbabic@denx.de> | Sun Nov 01 15:53:29 2020 +0100 |
| tree | 27367f31a98148fd5423a2a09e995601d521b094 | |
| parent | 538723e01234a6df0de54e902ca28c6db5b5c599 [diff] |
mx7ulp: clock: Align the PLL_USB frequency The command 'clocks' shows the following output: => clocks PLL_A7_SPLL 528 MHz PLL_A7_APLL 529 MHz PLL_USB 0 MHz Add some extra spaces so that the PLL_USB information gets aligned with the previous reported frequencies. Signed-off-by: Fabio Estevam <festevam@gmail.com>