tree 27367f31a98148fd5423a2a09e995601d521b094
parent 538723e01234a6df0de54e902ca28c6db5b5c599
author Fabio Estevam <festevam@gmail.com> 1602068972 -0300
committer Stefano Babic <sbabic@denx.de> 1604242409 +0100

mx7ulp: clock: Align the PLL_USB frequency

The command 'clocks' shows the following output:

=> clocks
PLL_A7_SPLL         528 MHz
PLL_A7_APLL         529 MHz
PLL_USB           0 MHz

Add some extra spaces so that the PLL_USB information gets aligned with
the previous reported frequencies.

Signed-off-by: Fabio Estevam <festevam@gmail.com>