| /* |
| * (C) Copyright 2001 |
| * |
| * See file CREDITS for list of people who contributed to this |
| * project. |
| * |
| * This program is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License as |
| * published by the Free Software Foundation; either version 2 of |
| * the License, or (at your option) any later version. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| * MA 02111-1307 USA |
| */ |
| |
| #include <common.h> |
| #include <asm/processor.h> |
| #include <command.h> |
| #include <malloc.h> |
| #include <spd_sdram.h> |
| |
| |
| int board_early_init_f (void) |
| { |
| /* |
| * IRQ 0-15 405GP internally generated; active high; level sensitive |
| * IRQ 16 405GP internally generated; active low; level sensitive |
| * IRQ 17-24 RESERVED |
| * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive |
| * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive |
| * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive |
| * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive |
| * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive |
| * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive |
| * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive |
| */ |
| mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
| mtdcr(UIC0ER, 0x00000000); /* disable all ints */ |
| mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ |
| mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ |
| mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ |
| mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ |
| mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
| |
| /* |
| * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us |
| */ |
| mtebc (EBC0_CFG, 0xa8400000); |
| |
| return 0; |
| } |
| |
| |
| /* ------------------------------------------------------------------------- */ |
| |
| int misc_init_f (void) |
| { |
| return 0; /* dummy implementation */ |
| } |
| |
| |
| int misc_init_r (void) |
| { |
| return (0); |
| } |
| |
| |
| /* |
| * Check Board Identity: |
| */ |
| |
| int checkboard (void) |
| { |
| char str[64]; |
| int i = getenv_r ("serial#", str, sizeof(str)); |
| |
| puts ("Board: "); |
| |
| if (i == -1) { |
| puts ("### No HW ID - assuming sbc405"); |
| } else { |
| puts(str); |
| } |
| |
| putc ('\n'); |
| |
| return 0; |
| } |
| |
| /* ------------------------------------------------------------------------- */ |
| |
| phys_size_t initdram (int board_type) |
| { |
| return spd_sdram (); |
| } |
| |
| /* ------------------------------------------------------------------------- */ |
| |
| int testdram (void) |
| { |
| /* TODO: XXX XXX XXX */ |
| printf ("test: 64 MB - ok\n"); |
| |
| return (0); |
| } |
| |
| /* ------------------------------------------------------------------------- */ |