| /* |
| * include/asm-arm/macro.h |
| * |
| * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
| * |
| * SPDX-License-Identifier: GPL-2.0+ |
| */ |
| |
| #ifndef __ASM_ARM_MACRO_H__ |
| #define __ASM_ARM_MACRO_H__ |
| #ifdef __ASSEMBLY__ |
| |
| /* |
| * These macros provide a convenient way to write 8, 16 and 32 bit data |
| * to any address. |
| * Registers r4 and r5 are used, any data in these registers are |
| * overwritten by the macros. |
| * The macros are valid for any ARM architecture, they do not implement |
| * any memory barriers so caution is recommended when using these when the |
| * caches are enabled or on a multi-core system. |
| */ |
| |
| .macro write32, addr, data |
| ldr r4, =\addr |
| ldr r5, =\data |
| str r5, [r4] |
| .endm |
| |
| .macro write16, addr, data |
| ldr r4, =\addr |
| ldrh r5, =\data |
| strh r5, [r4] |
| .endm |
| |
| .macro write8, addr, data |
| ldr r4, =\addr |
| ldrb r5, =\data |
| strb r5, [r4] |
| .endm |
| |
| /* |
| * This macro generates a loop that can be used for delays in the code. |
| * Register r4 is used, any data in this register is overwritten by the |
| * macro. |
| * The macro is valid for any ARM architeture. The actual time spent in the |
| * loop will vary from CPU to CPU though. |
| */ |
| |
| .macro wait_timer, time |
| ldr r4, =\time |
| 1: |
| nop |
| subs r4, r4, #1 |
| bcs 1b |
| .endm |
| |
| #endif /* __ASSEMBLY__ */ |
| #endif /* __ASM_ARM_MACRO_H__ */ |