Merge branch 'dcc' of git://www.denx.de/git/u-boot-microblaze
diff --git a/MAINTAINERS b/MAINTAINERS
index c6fd555..4297fe1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -472,6 +472,10 @@
P2020COME P2020
+York Sun <yorksun@freescale.com>
+
+ T4240EMU T4240
+
Timur Tabi <timur@freescale.com>
MPC8349E-mITX MPC8349
@@ -539,6 +543,10 @@
inka4x0 MPC5200
+Po Liu <po.liu@freescale.com>
+
+ C29XPCIE C29X
+
-------------------------------------------------------------------------
Unknown / orphaned boards:
diff --git a/README b/README
index a5c3e8d..3918807 100644
--- a/README
+++ b/README
@@ -406,13 +406,25 @@
This is the value to write into CCSR offset 0x18600
according to the A004510 workaround.
+ CONFIG_SYS_FSL_DSP_DDR_ADDR
+ This value denotes start offset of DDR memory which is
+ connected exclusively to the DSP cores.
+
CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
This value denotes start offset of M2 memory
which is directly connected to the DSP core.
+ CONFIG_SYS_FSL_DSP_M3_RAM_ADDR
+ This value denotes start offset of M3 memory which is directly
+ connected to the DSP core.
+
CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
This value denotes start offset of DSP CCSR space.
+ CONFIG_SYS_FSL_DDR_EMU
+ Specify emulator support for DDR. Some DDR features such as
+ deskew training are not available.
+
- Generic CPU options:
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index 02f5f8a..2dfcc2e 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -78,4 +78,5 @@
#define USB0_OTG_BASE 0x47401000
#define USB1_OTG_BASE 0x47401800
+int clk_get(int clk);
#endif /* __AM33XX_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-exynos/mipi_dsim.h b/arch/arm/include/asm/arch-exynos/mipi_dsim.h
index 8916d9d..498a9ff 100644
--- a/arch/arm/include/asm/arch-exynos/mipi_dsim.h
+++ b/arch/arm/include/asm/arch-exynos/mipi_dsim.h
@@ -291,7 +291,7 @@
*/
struct mipi_dsim_master_ops {
int (*cmd_write)(struct mipi_dsim_device *dsim, unsigned int data_id,
- unsigned int data0, unsigned int data1);
+ const unsigned char *data0, unsigned int data1);
int (*cmd_read)(struct mipi_dsim_device *dsim, unsigned int data_id,
unsigned int data0, unsigned int data1);
int (*get_dsim_frame_done)(struct mipi_dsim_device *dsim);
diff --git a/arch/arm/include/asm/imx-common/dma.h b/arch/arm/include/asm/imx-common/dma.h
index 5f516ef..d5c1f7f 100644
--- a/arch/arm/include/asm/imx-common/dma.h
+++ b/arch/arm/include/asm/imx-common/dma.h
@@ -161,4 +161,6 @@
int mxs_dma_init_channel(int chan);
int mxs_dma_release(int chan);
+void mxs_dma_circ_start(int chan, struct mxs_dma_desc *pdesc);
+
#endif /* __DMA_H__ */
diff --git a/arch/mips/include/asm/config.h b/arch/mips/include/asm/config.h
index cd29734..3a891ba 100644
--- a/arch/mips/include/asm/config.h
+++ b/arch/mips/include/asm/config.h
@@ -7,4 +7,7 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
+#define CONFIG_LMB
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
#endif
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index e9f82f7..f91406c 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -19,11 +19,7 @@
SOBJS-y +=
COBJS-y += board.o
-ifeq ($(CONFIG_QEMU_MIPS),y)
-COBJS-$(CONFIG_CMD_BOOTM) += bootm_qemu_mips.o
-else
COBJS-$(CONFIG_CMD_BOOTM) += bootm.o
-endif
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index ade9af4..66340ea 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -17,23 +17,148 @@
#define LINUX_MAX_ENVS 256
#define LINUX_MAX_ARGS 256
+#if defined(CONFIG_QEMU_MALTA)
+#define mips_boot_qemu_malta 1
+#else
+#define mips_boot_qemu_malta 0
+#endif
+
static int linux_argc;
static char **linux_argv;
+static char *linux_argp;
static char **linux_env;
static char *linux_env_p;
static int linux_env_idx;
-static void linux_params_init(ulong start, char *commandline);
-static void linux_env_set(char *env_name, char *env_val);
+static ulong arch_get_sp(void)
+{
+ ulong ret;
+
+ __asm__ __volatile__("move %0, $sp" : "=r"(ret) : );
+
+ return ret;
+}
+
+void arch_lmb_reserve(struct lmb *lmb)
+{
+ ulong sp;
+
+ sp = arch_get_sp();
+ debug("## Current stack ends at 0x%08lx\n", sp);
+
+ /* adjust sp by 4K to be safe */
+ sp -= 4096;
+ lmb_reserve(lmb, sp, CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp);
+}
+
+static void linux_cmdline_init(void)
+{
+ linux_argc = 1;
+ linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params);
+ linux_argv[0] = 0;
+ linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
+}
+
+static void linux_cmdline_set(const char *value, size_t len)
+{
+ linux_argv[linux_argc] = linux_argp;
+ memcpy(linux_argp, value, len);
+ linux_argp[len] = 0;
+
+ linux_argp += len + 1;
+ linux_argc++;
+}
+
+static void linux_cmdline_dump(void)
+{
+ int i;
+
+ debug("## cmdline argv at 0x%p, argp at 0x%p\n",
+ linux_argv, linux_argp);
+
+ for (i = 1; i < linux_argc; i++)
+ debug(" arg %03d: %s\n", i, linux_argv[i]);
+}
+
+static void boot_cmdline_linux(bootm_headers_t *images)
+{
+ const char *bootargs, *next, *quote;
+
+ linux_cmdline_init();
+
+ bootargs = getenv("bootargs");
+ if (!bootargs)
+ return;
+
+ next = bootargs;
+
+ while (bootargs && *bootargs && linux_argc < LINUX_MAX_ARGS) {
+ quote = strchr(bootargs, '"');
+ next = strchr(bootargs, ' ');
+
+ while (next && quote && quote < next) {
+ /*
+ * we found a left quote before the next blank
+ * now we have to find the matching right quote
+ */
+ next = strchr(quote + 1, '"');
+ if (next) {
+ quote = strchr(next + 1, '"');
+ next = strchr(next + 1, ' ');
+ }
+ }
+
+ if (!next)
+ next = bootargs + strlen(bootargs);
+
+ linux_cmdline_set(bootargs, next - bootargs);
+
+ if (*next)
+ next++;
+
+ bootargs = next;
+ }
+
+ linux_cmdline_dump();
+}
+
+static void linux_env_init(void)
+{
+ linux_env = (char **)(((ulong) linux_argp + 15) & ~15);
+ linux_env[0] = 0;
+ linux_env_p = (char *)(linux_env + LINUX_MAX_ENVS);
+ linux_env_idx = 0;
+}
+
+static void linux_env_set(const char *env_name, const char *env_val)
+{
+ if (linux_env_idx < LINUX_MAX_ENVS - 1) {
+ linux_env[linux_env_idx] = linux_env_p;
+
+ strcpy(linux_env_p, env_name);
+ linux_env_p += strlen(env_name);
+
+ if (mips_boot_qemu_malta) {
+ linux_env_p++;
+ linux_env[++linux_env_idx] = linux_env_p;
+ } else {
+ *linux_env_p++ = '=';
+ }
+
+ strcpy(linux_env_p, env_val);
+ linux_env_p += strlen(env_val);
+
+ linux_env_p++;
+ linux_env[++linux_env_idx] = 0;
+ }
+}
static void boot_prep_linux(bootm_headers_t *images)
{
- char *commandline = getenv("bootargs");
char env_buf[12];
- char *cp;
-
- linux_params_init(UNCACHED_SDRAM(gd->bd->bi_boot_params), commandline);
+ const char *cp;
+ ulong rd_start, rd_size;
#ifdef CONFIG_MEMSIZE_IN_BYTES
sprintf(env_buf, "%lu", (ulong)gd->ram_size);
@@ -41,15 +166,20 @@
#else
sprintf(env_buf, "%lu", (ulong)(gd->ram_size >> 20));
debug("## Giving linux memsize in MB, %lu\n",
- (ulong)(gd->ram_size >> 20));
+ (ulong)(gd->ram_size >> 20));
#endif /* CONFIG_MEMSIZE_IN_BYTES */
+ rd_start = UNCACHED_SDRAM(images->initrd_start);
+ rd_size = images->initrd_end - images->initrd_start;
+
+ linux_env_init();
+
linux_env_set("memsize", env_buf);
- sprintf(env_buf, "0x%08X", (uint) UNCACHED_SDRAM(images->rd_start));
+ sprintf(env_buf, "0x%08lX", rd_start);
linux_env_set("initrd_start", env_buf);
- sprintf(env_buf, "0x%X", (uint) (images->rd_end - images->rd_start));
+ sprintf(env_buf, "0x%lX", rd_size);
linux_env_set("initrd_size", env_buf);
sprintf(env_buf, "0x%08X", (uint) (gd->bd->bi_flashstart));
@@ -65,33 +195,42 @@
cp = getenv("eth1addr");
if (cp)
linux_env_set("eth1addr", cp);
+
+ if (mips_boot_qemu_malta)
+ linux_env_set("modetty0", "38400n8r");
}
static void boot_jump_linux(bootm_headers_t *images)
{
- void (*theKernel) (int, char **, char **, int *);
+ typedef void __noreturn (*kernel_entry_t)(int, ulong, ulong, ulong);
+ kernel_entry_t kernel = (kernel_entry_t) images->ep;
+ ulong linux_extra = 0;
- /* find kernel entry point */
- theKernel = (void (*)(int, char **, char **, int *))images->ep;
-
- debug("## Transferring control to Linux (at address %08lx) ...\n",
- (ulong) theKernel);
+ debug("## Transferring control to Linux (at address %p) ...\n", kernel);
bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+ if (mips_boot_qemu_malta)
+ linux_extra = gd->ram_size;
+
/* we assume that the kernel is in place */
printf("\nStarting kernel ...\n\n");
- theKernel(linux_argc, linux_argv, linux_env, 0);
+ kernel(linux_argc, (ulong)linux_argv, (ulong)linux_env, linux_extra);
}
int do_bootm_linux(int flag, int argc, char * const argv[],
bootm_headers_t *images)
{
/* No need for those on MIPS */
- if (flag & BOOTM_STATE_OS_BD_T || flag & BOOTM_STATE_OS_CMDLINE)
+ if (flag & BOOTM_STATE_OS_BD_T)
return -1;
+ if (flag & BOOTM_STATE_OS_CMDLINE) {
+ boot_cmdline_linux(images);
+ return 0;
+ }
+
if (flag & BOOTM_STATE_OS_PREP) {
boot_prep_linux(images);
return 0;
@@ -102,76 +241,10 @@
return 0;
}
+ boot_cmdline_linux(images);
boot_prep_linux(images);
boot_jump_linux(images);
/* does not return */
return 1;
}
-
-static void linux_params_init(ulong start, char *line)
-{
- char *next, *quote, *argp;
-
- linux_argc = 1;
- linux_argv = (char **) start;
- linux_argv[0] = 0;
- argp = (char *) (linux_argv + LINUX_MAX_ARGS);
-
- next = line;
-
- while (line && *line && linux_argc < LINUX_MAX_ARGS) {
- quote = strchr(line, '"');
- next = strchr(line, ' ');
-
- while (next && quote && quote < next) {
- /* we found a left quote before the next blank
- * now we have to find the matching right quote
- */
- next = strchr(quote + 1, '"');
- if (next) {
- quote = strchr(next + 1, '"');
- next = strchr(next + 1, ' ');
- }
- }
-
- if (!next)
- next = line + strlen(line);
-
- linux_argv[linux_argc] = argp;
- memcpy(argp, line, next - line);
- argp[next - line] = 0;
-
- argp += next - line + 1;
- linux_argc++;
-
- if (*next)
- next++;
-
- line = next;
- }
-
- linux_env = (char **) (((ulong) argp + 15) & ~15);
- linux_env[0] = 0;
- linux_env_p = (char *) (linux_env + LINUX_MAX_ENVS);
- linux_env_idx = 0;
-}
-
-static void linux_env_set(char *env_name, char *env_val)
-{
- if (linux_env_idx < LINUX_MAX_ENVS - 1) {
- linux_env[linux_env_idx] = linux_env_p;
-
- strcpy(linux_env_p, env_name);
- linux_env_p += strlen(env_name);
-
- strcpy(linux_env_p, "=");
- linux_env_p += 1;
-
- strcpy(linux_env_p, env_val);
- linux_env_p += strlen(env_val);
-
- linux_env_p++;
- linux_env[++linux_env_idx] = 0;
- }
-}
diff --git a/arch/mips/lib/bootm_qemu_mips.c b/arch/mips/lib/bootm_qemu_mips.c
deleted file mode 100644
index 910ab73..0000000
--- a/arch/mips/lib/bootm_qemu_mips.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * (C) Copyright 2008
- * Jean-Christophe PLAGNIOL-VILLARD <jcplagniol@jcrosoft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <image.h>
-#include <asm/byteorder.h>
-#include <asm/addrspace.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int do_bootm_linux(int flag, int argc, char * const argv[],
- bootm_headers_t *images)
-{
- void (*theKernel) (int, char **, char **, int *);
- char *bootargs = getenv("bootargs");
- char *start;
- uint len;
-
- /* find kernel entry point */
- theKernel = (void (*)(int, char **, char **, int *))images->ep;
-
- bootstage_mark(BOOTSTAGE_ID_RUN_OS);
-
- debug("## Transferring control to Linux (at address %08lx) ...\n",
- (ulong) theKernel);
-
- gd->bd->bi_boot_params = gd->bd->bi_memstart + (16 << 20) - 256;
- debug("%-12s= 0x%08lX\n", "boot_params", (ulong)gd->bd->bi_boot_params);
-
- /* set Magic */
- *(int32_t *)(gd->bd->bi_boot_params - 4) = 0x12345678;
- /* set ram_size */
- *(int32_t *)(gd->bd->bi_boot_params - 8) = gd->ram_size;
-
- start = (char *)gd->bd->bi_boot_params;
-
- len = strlen(bootargs);
-
- strncpy(start, bootargs, len + 1);
-
- start += len;
-
- len = images->rd_end - images->rd_start;
- if (len > 0) {
- start += sprintf(start, " rd_start=0x%08X rd_size=0x%0X",
- (uint) UNCACHED_SDRAM(images->rd_start),
- (uint) len);
- }
-
- /* we assume that the kernel is in place */
- printf("\nStarting kernel ...\n\n");
-
- theKernel(0, NULL, NULL, 0);
-
- /* does not return */
- return 1;
-}
diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c
index 09970b0..28c25e5 100644
--- a/arch/powerpc/cpu/mpc83xx/pcie.c
+++ b/arch/powerpc/cpu/mpc83xx/pcie.c
@@ -299,6 +299,8 @@
printf("PCIE%d: ", bus);
+#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
+#define PCI_LTSSM_L0 0x16 /* L0 state */
reg16 = in_le16(hose_cfg_base + PCI_LTSSM);
if (reg16 >= PCI_LTSSM_L0)
printf("link\n");
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 0d1e8f1..f70f0d7 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -46,6 +46,7 @@
COBJS-$(CONFIG_MPC8544) += ddr-gen2.o
# supports ddr1/2/3
+COBJS-$(CONFIG_PPC_C29X) += ddr-gen3.o
COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
COBJS-$(CONFIG_MPC8569) += ddr-gen3.o
@@ -100,6 +101,7 @@
COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
# SoC specific SERDES support
+COBJS-$(CONFIG_PPC_C29X) += c29x_serdes.o
COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
COBJS-$(CONFIG_MPC8544) += mpc8544_serdes.o
COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
index 53c6a7f..39b8e3e 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
@@ -41,8 +41,8 @@
#ifdef CONFIG_SYS_SRIO
struct srio_liodn_id_table srio_liodn_tbl[] = {
- SET_SRIO_LIODN_1(1, 307),
- SET_SRIO_LIODN_1(2, 387),
+ SET_SRIO_LIODN_BASE(1, 307),
+ SET_SRIO_LIODN_BASE(2, 387),
};
int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
#endif
@@ -112,10 +112,10 @@
#ifdef CONFIG_SYS_DPAA_RMAN
struct liodn_id_table rman_liodn_tbl[] = {
/* Set RMan block 0-3 liodn offset */
- SET_RMAN_LIODN(0, 678),
- SET_RMAN_LIODN(1, 679),
- SET_RMAN_LIODN(2, 680),
- SET_RMAN_LIODN(3, 681),
+ SET_RMAN_LIODN(0, 6),
+ SET_RMAN_LIODN(1, 7),
+ SET_RMAN_LIODN(2, 8),
+ SET_RMAN_LIODN(3, 9),
};
int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c
new file mode 100644
index 0000000..51972cb
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+#define SRDS1_MAX_LANES 4
+
+static u32 serdes1_prtcl_map;
+
+struct serdes_config {
+ u32 protocol;
+ u8 lanes[SRDS1_MAX_LANES];
+};
+
+static const struct serdes_config serdes1_cfg_tbl[] = {
+ /* SerDes 1 */
+ {1, {PCIE1, PCIE1, PCIE1, PCIE1} },
+ {2, {PCIE1, PCIE1, PCIE1, PCIE1} },
+ {3, {PCIE1, PCIE1, NONE, NONE} },
+ {4, {PCIE1, PCIE1, NONE, NONE} },
+ {5, {PCIE1, NONE, NONE, NONE} },
+ {6, {PCIE1, NONE, NONE, NONE} },
+ {}
+};
+
+int is_serdes_configured(enum srds_prtcl device)
+{
+ return (1 << device) & serdes1_prtcl_map;
+}
+
+void fsl_serdes_init(void)
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ u32 pordevsr = in_be32(&gur->pordevsr);
+ u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+ MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+ const struct serdes_config *ptr;
+ int lane;
+
+ debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
+
+ if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+ printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
+ return;
+ }
+
+ ptr = &serdes1_cfg_tbl[srds_cfg];
+ if (!ptr->protocol)
+ return;
+
+ for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = ptr->lanes[lane];
+ serdes1_prtcl_map |= (1 << lane_prtcl);
+ }
+}
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 5cd02cc..cbb443f 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -245,6 +245,9 @@
#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
puts("Work-around for Erratum A006593 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
+ puts("Work-around for Erratum A-005812 enabled\n");
+#endif
return 0;
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 91ac4ee..66bc6a2 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -44,10 +44,10 @@
uint major, minor;
struct cpu_type *cpu;
char buf1[32], buf2[32];
-#if (defined(CONFIG_DDR_CLK_FREQ) || \
- defined(CONFIG_FSL_CORENET)) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#endif /* CONFIG_FSL_CORENET */
+#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
+ ccsr_gur_t __iomem *gur =
+ (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
/*
* Cornet platforms use ddr sync bit in RCW to indicate sync vs async
@@ -211,6 +211,21 @@
puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
+#ifdef CONFIG_FSL_CORENET
+ /* Display the RCW, so that no one gets confused as to what RCW
+ * we're actually using for this boot.
+ */
+ puts("Reset Configuration Word (RCW):");
+ for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
+ u32 rcw = in_be32(&gur->rcwsr[i]);
+
+ if ((i % 4) == 0)
+ printf("\n %08x:", i * 4);
+ printf(" %08x", rcw);
+ }
+ puts("\n");
+#endif
+
return 0;
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 25beda2..48b3826 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -399,6 +399,14 @@
sync();
}
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
+ /*
+ * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
+ * in write shadow mode. Checking DCWS before setting SPR 976.
+ */
+ if (mfspr(L1CSR2) & L1CSR2_DCWS)
+ mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
+#endif
#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
spin = getenv("spin_table_compat");
@@ -532,8 +540,10 @@
enable_cpc();
+#ifndef CONFIG_SYS_FSL_NO_SERDES
/* needs to be in ram since code uses global static vars */
fsl_serdes_init();
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
if (IS_SVR_REV(svr, 1, 0)) {
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen1.c b/arch/powerpc/cpu/mpc85xx/ddr-gen1.c
index 8a86819..4dd8c0b 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen1.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen1.c
@@ -15,7 +15,7 @@
#endif
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
- unsigned int ctrl_num)
+ unsigned int ctrl_num, int step)
{
unsigned int i;
volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
index a705862..542bc84 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
@@ -16,7 +16,7 @@
#endif
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
- unsigned int ctrl_num)
+ unsigned int ctrl_num, int step)
{
unsigned int i;
ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
index c5b4720..1be51d3 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
@@ -15,8 +15,18 @@
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
#endif
+
+/*
+ * regs has the to-be-set values for DDR controller registers
+ * ctrl_num is the DDR controller number
+ * step: 0 goes through the initialization in one pass
+ * 1 sets registers and returns before enabling controller
+ * 2 resumes from step 1 and continues to initialize
+ * Dividing the initialization to two steps to deassert DDR reset signal
+ * to comply with JEDEC specs for RDIMMs.
+ */
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
- unsigned int ctrl_num)
+ unsigned int ctrl_num, int step)
{
unsigned int i, bus_width;
volatile ccsr_ddr_t *ddr;
@@ -54,6 +64,9 @@
return;
}
+ if (step == 2)
+ goto step2;
+
if (regs->ddr_eor)
out_be32(&ddr->eor, regs->ddr_eor);
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
@@ -123,10 +136,17 @@
out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
+#ifndef CONFIG_SYS_FSL_DDR_EMU
+ /*
+ * Skip these two registers if running on emulator
+ * because emulator doesn't have skew between bytes.
+ */
+
if (regs->ddr_wrlvl_cntl_2)
out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
if (regs->ddr_wrlvl_cntl_3)
out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
+#endif
out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
@@ -150,6 +170,20 @@
out_be32(&ddr->debug[21], 0x24000000);
#endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
+ /*
+ * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
+ * deasserted. Clocks start when any chip select is enabled and clock
+ * control register is set. Because all DDR components are connected to
+ * one reset signal, this needs to be done in two steps. Step 1 is to
+ * get the clocks started. Step 2 resumes after reset signal is
+ * deasserted.
+ */
+ if (step == 1) {
+ udelay(200);
+ return;
+ }
+
+step2:
/* Set, but do not enable the memory */
temp_sdram_cfg = regs->ddr_sdram_cfg;
temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index cfaa2ed..84bb8fa 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -604,8 +604,12 @@
fdt_add_enet_stashing(blob);
+#ifndef CONFIG_FSL_TBCLK_EXTRA_DIV
+#define CONFIG_FSL_TBCLK_EXTRA_DIV 1
+#endif
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
- "timebase-frequency", get_tbclk(), 1);
+ "timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV,
+ 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"bus-frequency", bd->bi_busfreq, 1);
get_sys_info(&sysinfo);
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h
index 6de572d..d515b23 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h
@@ -9,5 +9,4 @@
int is_serdes_prtcl_valid(int serdes, u32 prtcl);
int serdes_lane_enabled(int lane);
-enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
#endif /* __FSL_CORENET2_SERDES_H */
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index 15bbbc1..c15e83b 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -226,6 +226,21 @@
2:
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
+ /*
+ * A-005812 workaround sets bit 32 of SPR 976 for SoCs running in
+ * write shadow mode. This code should run after other code setting
+ * DCWS.
+ */
+ mfspr r3,L1CSR2
+ andis. r3,r3,(L1CSR2_DCWS)@h
+ beq 1f
+ mfspr r3, SPRN_HDBCR0
+ oris r3, r3, 0x8000
+ mtspr SPRN_HDBCR0, r3
+1:
+#endif
+
#ifdef CONFIG_BACKSIDE_L2_CACHE
/* skip L2 setup on P2040/P2040E as they have no L2 */
mfspr r3,SPRN_SVR
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index cfc3a60..ad57a9c 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -33,7 +33,8 @@
#define MINIMAL_SPL
#endif
-#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
+#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && \
+ !defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
#define NOR_BOOT
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c
index e173cb5..54c1cfd 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c
@@ -65,8 +65,8 @@
#endif
struct srio_liodn_id_table srio_liodn_tbl[] = {
- SET_SRIO_LIODN_1(1, 307),
- SET_SRIO_LIODN_1(2, 387),
+ SET_SRIO_LIODN_BASE(1, 307),
+ SET_SRIO_LIODN_BASE(2, 387),
};
int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
@@ -159,10 +159,10 @@
#ifdef CONFIG_SYS_DPAA_RMAN
struct liodn_id_table rman_liodn_tbl[] = {
/* Set RMan block 0-3 liodn offset */
- SET_RMAN_LIODN(0, 678),
- SET_RMAN_LIODN(1, 679),
- SET_RMAN_LIODN(2, 680),
- SET_RMAN_LIODN(3, 681),
+ SET_RMAN_LIODN(0, 6),
+ SET_RMAN_LIODN(1, 7),
+ SET_RMAN_LIODN(2, 8),
+ SET_RMAN_LIODN(3, 9),
};
int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
#endif
diff --git a/arch/powerpc/cpu/mpc86xx/ddr-8641.c b/arch/powerpc/cpu/mpc86xx/ddr-8641.c
index 92ba26d..33a91f9 100644
--- a/arch/powerpc/cpu/mpc86xx/ddr-8641.c
+++ b/arch/powerpc/cpu/mpc86xx/ddr-8641.c
@@ -15,7 +15,7 @@
#endif
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
- unsigned int ctrl_num)
+ unsigned int ctrl_num, int step)
{
unsigned int i;
volatile ccsr_ddr_t *ddr;
diff --git a/arch/powerpc/cpu/mpc8xx/video.c b/arch/powerpc/cpu/mpc8xx/video.c
index 02cd0de..02a0467 100644
--- a/arch/powerpc/cpu/mpc8xx/video.c
+++ b/arch/powerpc/cpu/mpc8xx/video.c
@@ -109,7 +109,6 @@
/************************************************************************/
#include <video_font.h> /* Get font data, width and height */
-#include <video_font_data.h>
#ifdef CONFIG_VIDEO_LOGO
#include <video_logo.h> /* Get logo data, width and height */
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 7369582..c67be4e 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -79,6 +79,9 @@
CPU_TYPE_ENTRY(BSC9131, 9131, 1),
CPU_TYPE_ENTRY(BSC9132, 9132, 2),
CPU_TYPE_ENTRY(BSC9232, 9232, 2),
+ CPU_TYPE_ENTRY(C291, C291, 1),
+ CPU_TYPE_ENTRY(C292, C292, 1),
+ CPU_TYPE_ENTRY(C293, C293, 1),
#elif defined(CONFIG_MPC86xx)
CPU_TYPE_ENTRY(8610, 8610, 1),
CPU_TYPE_ENTRY(8641, 8641, 2),
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index ff5812d..242eb47 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -364,7 +364,7 @@
ddr->timing_cfg_3 = (0
| ((ext_pretoact & 0x1) << 28)
- | ((ext_acttopre & 0x2) << 24)
+ | ((ext_acttopre & 0x3) << 24)
| ((ext_acttorw & 0x1) << 22)
| ((ext_refrec & 0x1F) << 16)
| ((ext_caslat & 0x3) << 12)
@@ -681,6 +681,7 @@
unsigned int odt_cfg = 0; /* ODT configuration */
unsigned int num_pr; /* Number of posted refreshes */
unsigned int slow = 0; /* DDR will be run less than 1250 */
+ unsigned int x4_en = 0; /* x4 DRAM enable */
unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
unsigned int ap_en; /* Address Parity Enable */
unsigned int d_init; /* DRAM data initialization */
@@ -725,6 +726,8 @@
ap_en = 0;
}
+ x4_en = popts->x4_en ? 1 : 0;
+
#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/* Use the DDR controller to auto initialize memory. */
d_init = popts->ECC_init_using_memctl;
@@ -747,6 +750,7 @@
| ((odt_cfg & 0x3) << 21)
| ((num_pr & 0xf) << 12)
| ((slow & 1) << 11)
+ | (x4_en << 10)
| (qd_en << 9)
| (unq_mrs_en << 8)
| ((obc_cfg & 0x1) << 6)
@@ -1585,8 +1589,8 @@
| ((ea & 0xFFF) << 0) /* ending address MSB */
);
} else {
- debug("FSLDDR: setting bnds to 0 for inactive CS\n");
- ddr->cs[i].bnds = 0;
+ /* setting bnds to 0xffffffff for inactive CS */
+ ddr->cs[i].bnds = 0xffffffff;
}
debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
@@ -1638,5 +1642,10 @@
set_ddr_sdram_rcw(ddr, popts, common_dimm);
+#ifdef CONFIG_SYS_FSL_DDR_EMU
+ /* disble DDR training for emulator */
+ ddr->debug[2] = 0x00000400;
+ ddr->debug[4] = 0xff800000;
+#endif
return check_fsl_memctl_config_regs(ddr);
}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
index 4dd55fc..c173a5a 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
@@ -96,7 +96,7 @@
/* processor specific function */
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
- unsigned int ctrl_num);
+ unsigned int ctrl_num, int step);
/* board specific function */
int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
index 3e7c269..b67158c 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
@@ -129,6 +129,7 @@
pdimm->ec_sdram_width = 0;
pdimm->data_width = pdimm->primary_sdram_width
+ pdimm->ec_sdram_width;
+ pdimm->device_width = 1 << ((spd->organization & 0x7) + 2);
/* These are the types defined by the JEDEC DDR3 SPD spec */
pdimm->mirrored_dimm = 0;
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
index 1ed6c77..260fce5 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
@@ -205,6 +205,7 @@
DIMM_PARM(primary_sdram_width),
DIMM_PARM(ec_sdram_width),
DIMM_PARM(registered_dimm),
+ DIMM_PARM(device_width),
DIMM_PARM(n_row_addr),
DIMM_PARM(n_col_addr),
@@ -263,6 +264,7 @@
DIMM_PARM(primary_sdram_width),
DIMM_PARM(ec_sdram_width),
DIMM_PARM(registered_dimm),
+ DIMM_PARM(device_width),
DIMM_PARM(n_row_addr),
DIMM_PARM(n_col_addr),
@@ -443,6 +445,7 @@
CTRL_OPTIONS(twoT_en),
CTRL_OPTIONS(threeT_en),
CTRL_OPTIONS(ap_en),
+ CTRL_OPTIONS(x4_en),
CTRL_OPTIONS(bstopre),
CTRL_OPTIONS(wrlvl_override),
CTRL_OPTIONS(wrlvl_sample),
@@ -687,6 +690,7 @@
CTRL_OPTIONS(threeT_en),
CTRL_OPTIONS(registered_dimm_en),
CTRL_OPTIONS(ap_en),
+ CTRL_OPTIONS(x4_en),
CTRL_OPTIONS(bstopre),
CTRL_OPTIONS(wrlvl_override),
CTRL_OPTIONS(wrlvl_sample),
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index 7a8636d..9f4f253 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -25,10 +25,6 @@
unsigned int ctrl_num);
void fsl_ddr_set_intl3r(const unsigned int granule_size);
-/* processor specific function */
-extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
- unsigned int ctrl_num);
-
#if defined(SPD_EEPROM_ADDRESS) || \
defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
@@ -365,9 +361,11 @@
{
unsigned int i, j;
unsigned long long total_mem = 0;
+ int assert_reset;
fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
common_timing_params_t *timing_params = pinfo->common_timing_params;
+ assert_reset = board_need_mem_reset();
/* data bus width capacity adjust shift amount */
unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
@@ -462,7 +460,20 @@
timing_params[i].all_DIMMs_registered,
&pinfo->memctl_opts[i],
pinfo->dimm_params[i], i);
+ /*
+ * For RDIMMs, JEDEC spec requires clocks to be stable
+ * before reset signal is deasserted. For the boards
+ * using fixed parameters, this function should be
+ * be called from board init file.
+ */
+ if (timing_params[i].all_DIMMs_registered)
+ assert_reset = 1;
}
+ if (assert_reset) {
+ debug("Asserting mem reset\n");
+ board_assert_mem_reset();
+ }
+
case STEP_ASSIGN_ADDRESSES:
/* STEP 5: Assign addresses to chip selects */
check_interleaving_options(pinfo);
@@ -504,7 +515,13 @@
fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
if (reg->cs[j].config & 0x80000000) {
unsigned int end;
- end = reg->cs[j].bnds & 0xFFF;
+ /*
+ * 0xfffffff is a special value we put
+ * for unused bnds
+ */
+ if (reg->cs[j].bnds == 0xffffffff)
+ continue;
+ end = reg->cs[j].bnds & 0xffff;
if (end > max_end) {
max_end = end;
}
@@ -531,6 +548,7 @@
unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
unsigned long long total_memory;
fsl_ddr_info_t info;
+ int deassert_reset;
/* Reset info structure. */
memset(&info, 0, sizeof(fsl_ddr_info_t));
@@ -559,7 +577,21 @@
}
}
- /* Program configuration registers. */
+ /*
+ * Program configuration registers.
+ * JEDEC specs requires clocks to be stable before deasserting reset
+ * for RDIMMs. Clocks start after chip select is enabled and clock
+ * control register is set. During step 1, all controllers have their
+ * registers set but not enabled. Step 2 proceeds after deasserting
+ * reset through board FPGA or GPIO.
+ * For non-registered DIMMs, initialization can go through but it is
+ * also OK to follow the same flow.
+ */
+ deassert_reset = board_need_mem_reset();
+ for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ if (info.common_timing_params[i].all_DIMMs_registered)
+ deassert_reset = 1;
+ }
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
debug("Programming controller %u\n", i);
if (info.common_timing_params[i].ndimms_present == 0) {
@@ -567,8 +599,22 @@
"skipping programming\n", i);
continue;
}
-
- fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i);
+ /*
+ * The following call with step = 1 returns before enabling
+ * the controller. It has to finish with step = 2 later.
+ */
+ fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i,
+ deassert_reset ? 1 : 0);
+ }
+ if (deassert_reset) {
+ /* Use board FPGA or GPIO to deassert reset signal */
+ debug("Deasserting mem reset\n");
+ board_deassert_mem_reset();
+ for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ /* Call with step = 2 to continue initialization */
+ fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]),
+ i, 2);
+ }
}
/* program LAWs */
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
index 26369e0..30cdca4 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
@@ -700,6 +700,8 @@
}
#endif
+ popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0;
+
/* Choose burst length. */
#if defined(CONFIG_FSL_DDR3)
#if defined(CONFIG_E500MC)
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 7ed93ac..ce1bf05 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -303,6 +303,7 @@
#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
@@ -336,6 +337,7 @@
#elif defined(CONFIG_PPC_P3041)
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
@@ -366,9 +368,11 @@
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
#define CONFIG_SYS_FSL_ERRATUM_A004849
+#define CONFIG_SYS_FSL_ERRATUM_A005812
#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_MAX_CPUS 8
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
#define CONFIG_SYS_FSL_NUM_LAWS 32
@@ -410,10 +414,12 @@
#define CONFIG_SYS_FSL_ERRATUM_A004849
#define CONFIG_SYS_FSL_ERRATUM_A004580
#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
+#define CONFIG_SYS_FSL_ERRATUM_A005812
#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
#define CONFIG_SYS_PPC64 /* 64-bit core */
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
@@ -444,6 +450,7 @@
#elif defined(CONFIG_PPC_P5040)
#define CONFIG_SYS_PPC64
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
#define CONFIG_SYS_FSL_NUM_LAWS 32
@@ -469,6 +476,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A004510
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+#define CONFIG_SYS_FSL_ERRATUM_A005812
#elif defined(CONFIG_BSC9131)
#define CONFIG_MAX_CPUS 1
@@ -492,6 +500,10 @@
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_NUM_DDR_CONTROLLERS 2
+#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
+#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
+#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
+#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_NAND_FSL_IFC
@@ -536,6 +548,7 @@
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_SRIO_LIODN
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_A004468
@@ -576,6 +589,7 @@
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_SRIO_LIODN
#else
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
@@ -612,6 +626,18 @@
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
+#elif defined(CONFIG_PPC_C29X)
+#define CONFIG_MAX_CPUS 1
+#define CONFIG_FSL_SDHC_V2_3
+#define CONFIG_SYS_FSL_NUM_LAWS 12
+#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
+#define CONFIG_TSECV2_1
+#define CONFIG_SYS_FSL_SEC_COMPAT 6
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
+
#else
#error Processor type not defined for this platform
#endif
diff --git a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
index ffe4db8..bd312ad 100644
--- a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
+++ b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
@@ -26,6 +26,7 @@
unsigned int primary_sdram_width;
unsigned int ec_sdram_width;
unsigned int registered_dimm;
+ unsigned int device_width; /* x4, x8, x16 components */
/* SDRAM device parameters */
unsigned int n_row_addr;
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index 640d329..f4eec82 100644
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -277,6 +277,7 @@
unsigned int mirrored_dimm;
unsigned int quad_rank_present;
unsigned int ap_en; /* address parity enable for RDIMM */
+ unsigned int x4_en; /* enable x4 devices */
/* Global Timing Parameters */
unsigned int cas_latency_override;
@@ -330,9 +331,31 @@
extern phys_size_t fsl_ddr_sdram_size(void);
extern int fsl_use_spd(void);
extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
- unsigned int ctrl_num);
+ unsigned int ctrl_num, int step);
u32 fsl_ddr_get_intl3r(void);
+static void __board_assert_mem_reset(void)
+{
+}
+
+static void __board_deassert_mem_reset(void)
+{
+}
+
+void board_assert_mem_reset(void)
+ __attribute__((weak, alias("__board_assert_mem_reset")));
+
+void board_deassert_mem_reset(void)
+ __attribute__((weak, alias("__board_deassert_mem_reset")));
+
+static int __board_need_mem_reset(void)
+{
+ return 0;
+}
+
+int board_need_mem_reset(void)
+ __attribute__((weak, alias("__board_need_mem_reset")));
+
/*
* The 85xx boards have a common prototype for fixed_sdram so put the
* declaration here.
diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h
index bea1636..37d3a22 100644
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -82,7 +82,7 @@
#ifndef CONFIG_MPC8641
LAW_TRGT_IF_PCIE_1 = 0x02,
#endif
-#if defined(CONFIG_BSC9131)
+#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
LAW_TRGT_IF_OCN_DSP = 0x03,
#else
#if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020)
@@ -92,9 +92,14 @@
LAW_TRGT_IF_LBC = 0x04,
LAW_TRGT_IF_CCSR = 0x08,
LAW_TRGT_IF_DSP_CCSR = 0x09,
+ LAW_TRGT_IF_PLATFORM_SRAM = 0x0a,
LAW_TRGT_IF_DDR_INTRLV = 0x0b,
LAW_TRGT_IF_RIO = 0x0c,
+#if defined(CONFIG_BSC9132)
+ LAW_TRGT_IF_CLASS_DSP = 0x0d,
+#else
LAW_TRGT_IF_RIO_2 = 0x0d,
+#endif
LAW_TRGT_IF_DPAA_SWP_SRAM = 0x0e,
LAW_TRGT_IF_DDR = 0x0f,
LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index 3f543d9..44bc88d 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -29,6 +29,13 @@
+ CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
}
+#define SET_SRIO_LIODN_BASE(port, id_a) \
+ { .id = { id_a }, .num_ids = 1, .portid = port, \
+ .reg_offset[0] = offsetof(struct ccsr_rio, liodn) \
+ + (port - 1) * 0x200 \
+ + CONFIG_SYS_FSL_SRIO_ADDR, \
+ }
+
struct liodn_id_table {
const char * compat;
u32 id[2];
diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h
index c740da3..749411c 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
+ * Copyright 2007,2009-2012 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -13,6 +13,34 @@
#define PEX_IP_BLK_REV_2_2 0x02080202
#define PEX_IP_BLK_REV_2_3 0x02080203
+#define PEX_IP_BLK_REV_3_0 0x02080300
+
+/* Freescale-specific PCI config registers */
+#define FSL_PCI_PBFR 0x44
+
+#ifdef CONFIG_SYS_FSL_PCI_VER_3_X
+/* Currently only the PCIe capability is used, so hardcode the offset.
+ * if more capabilities need to be justified, the capability link method
+ * should be applied here
+ */
+#define FSL_PCIE_CAP_ID 0x70
+#define PCI_DCR 0x78 /* PCIe Device Control Register */
+#define PCI_DSR 0x7a /* PCIe Device Status Register */
+#define PCI_LSR 0x82 /* PCIe Link Status Register */
+#define PCI_LCR 0x80 /* PCIe Link Control Register */
+#else
+#define FSL_PCIE_CAP_ID 0x4c
+#define PCI_DCR 0x54 /* PCIe Device Control Register */
+#define PCI_DSR 0x56 /* PCIe Device Status Register */
+#define PCI_LSR 0x5e /* PCIe Link Status Register */
+#define PCI_LCR 0x5c /* PCIe Link Control Register */
+#endif
+
+#define FSL_PCIE_CFG_RDY 0x4b0
+#define FSL_PROG_IF_AGENT 0x1
+
+#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
+#define PCI_LTSSM_L0 0x16 /* L0 state */
int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
int fsl_is_pci_agent(struct pci_controller *hose);
@@ -149,7 +177,10 @@
u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */
char res23[200];
u32 pdb_stat; /* 0xf00 - PCIE Debug Status */
- char res24[252];
+ char res24[16];
+ u32 pex_csr0; /* 0xf14 - PEX Control/Status register 0*/
+ u32 pex_csr1; /* 0xf18 - PEX Control/Status register 1*/
+ char res25[228];
} ccsr_fsl_pci_t;
#define PCIE_CONFIG_PC 0x00020000
#define PCIE_CONFIG_OB_CK 0x00002000
diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
index 59189ad..1106d28 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -90,6 +90,7 @@
#ifdef CONFIG_FSL_CORENET
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
#else
int serdes_get_first_lane(enum srds_prtcl device);
#endif
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 81b3322..2ed384e 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1544,6 +1544,18 @@
};
#endif
+#ifdef CONFIG_SYS_FSL_SRIO_LIODN
+struct rio_liodn {
+ u32 plbr;
+ u8 res0[28];
+ u32 plaor;
+ u8 res1[12];
+ u32 pludr;
+ u32 plldr;
+ u8 res2[456];
+};
+#endif
+
/* RapidIO Registers */
struct ccsr_rio {
struct rio_arch arch;
@@ -1566,6 +1578,10 @@
u8 res7[100];
struct rio_pw pw;
#endif
+#ifdef CONFIG_SYS_FSL_SRIO_LIODN
+ u8 res5[8192];
+ struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+#endif
};
#endif
@@ -2131,6 +2147,11 @@
#ifdef CONFIG_MPC8536
#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
+#elif defined(CONFIG_PPC_C29X)
+#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
+#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \
+ & MPC85xx_PORDEVSR2_DDR_SPD_0) \
+ >> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
#else
#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
@@ -2178,6 +2199,9 @@
#elif defined(CONFIG_BSC9132)
#define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17
+#elif defined(CONFIG_PPC_C29X)
+#define MPC85xx_PORDEVSR_IO_SEL 0x00e00000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
#else
#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
@@ -2193,6 +2217,10 @@
#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
u32 pordbgmsr; /* POR debug mode status */
u32 pordevsr2; /* POR I/O device status 2 */
+#if defined(CONFIG_PPC_C29X)
+#define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008
+#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3
+#endif
/* The 8544 RM says this is bit 26, but it's really bit 24 */
#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
u8 res1[8];
@@ -2339,6 +2367,11 @@
#define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000
#define MPC85xx_PMUXCR0_SIM_SEL 0x00014000
#endif
+#if defined(CONFIG_PPC_C29X)
+#define MPC85xx_PMUXCR_SPI_MASK 0x00000300
+#define MPC85xx_PMUXCR_SPI 0x00000000
+#define MPC85xx_PMUXCR_SPI_GPIO 0x00000100
+#endif
u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
#if defined(CONFIG_P1010) || defined(CONFIG_P1014)
#define MPC85xx_PMUXCR2_UART_GPIO 0x40000000
@@ -2526,7 +2559,9 @@
#define SRDS_RSTCTL_RSTDONE 0x40000000
#define SRDS_RSTCTL_RSTERR 0x20000000
#define SRDS_RSTCTL_SWRST 0x10000000
-#define SRDS_RSTCTL_SDPD 0x00000020
+#define SRDS_RSTCTL_SDEN 0x00000020
+#define SRDS_RSTCTL_SDRST_B 0x00000040
+#define SRDS_RSTCTL_PLLRST_B 0x00000080
u32 pllcr0; /* PLL Control Register 0 */
#define SRDS_PLLCR0_POFF 0x80000000
#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
@@ -3008,12 +3043,18 @@
#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000
#ifdef CONFIG_TSECV2
#define CONFIG_SYS_TSEC1_OFFSET 0xB0000
+#elif defined(CONFIG_TSECV2_1)
+#define CONFIG_SYS_TSEC1_OFFSET 0x10000
#else
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#endif
#define CONFIG_SYS_MDIO1_OFFSET 0x24000
#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
+#if defined(CONFIG_PPC_C29X)
+#define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
+#else
#define CONFIG_SYS_FSL_SEC_OFFSET 0x30000
+#endif
#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
#define CONFIG_SYS_SNVS_OFFSET 0xE6000
@@ -3031,6 +3072,12 @@
#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
+#if defined(CONFIG_BSC9132)
+#define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000
+#define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \
+ (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET)
+#endif
+
#define CONFIG_SYS_FSL_CPC_ADDR \
(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
#define CONFIG_SYS_FSL_QMAN_ADDR \
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 56b22d8..64a6f9c 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1119,6 +1119,9 @@
#define SVR_T4240 0x824000
#define SVR_T4120 0x824001
#define SVR_T4160 0x824100
+#define SVR_C291 0x850000
+#define SVR_C292 0x850020
+#define SVR_C293 0x850030
#define SVR_B4860 0X868000
#define SVR_G4860 0x868001
#define SVR_G4060 0x868003
diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c
index c786997..c4444c7 100644
--- a/board/davinci/ea20/ea20.c
+++ b/board/davinci/ea20/ea20.c
@@ -24,7 +24,7 @@
#include <asm/io.h>
#include <asm/arch/davinci_misc.h>
#include <asm/gpio.h>
-#include <asm/arch/da8xx-fb.h>
+#include "../../../drivers/video/da8xx-fb.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -43,6 +43,30 @@
.invert_pxl_clk = 0,
};
+static const struct display_panel disp_panel = {
+ QVGA,
+ 16,
+ 16,
+ COLOR_ACTIVE,
+};
+
+static const struct lcd_ctrl_config lcd_cfg = {
+ &disp_panel,
+ .ac_bias = 255,
+ .ac_bias_intrpt = 0,
+ .dma_burst_sz = 16,
+ .bpp = 16,
+ .fdd = 255,
+ .tft_alt_mode = 0,
+ .stn_565_mode = 0,
+ .mono_8bit_mode = 0,
+ .invert_line_clock = 1,
+ .invert_frm_clock = 1,
+ .sync_edge = 0,
+ .sync_ctrl = 1,
+ .raster_order = 0,
+};
+
/* SPI0 pin muxer settings */
static const struct pinmux_config spi1_pins[] = {
{ pinmux(5), 1, 1 },
@@ -259,7 +283,7 @@
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
- da8xx_video_init(&lcd_panel, 16);
+ da8xx_video_init(&lcd_panel, &lcd_cfg, 16);
return 0;
}
diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
index 86e44ea..f74651c 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -21,12 +21,14 @@
#include "../common/qixis.h"
#include "../common/vsc3316_3308.h"
+#include "../common/idt8t49n222a_serdes_clk.h"
#include "b4860qds.h"
#include "b4860qds_qixis.h"
#include "b4860qds_crossbar_con.h"
#define CLK_MUX_SEL_MASK 0x4
#define ETH_PHY_CLK_OUT 0x4
+#define PLL_NUM 2
DECLARE_GLOBAL_DATA_PTR;
@@ -35,8 +37,6 @@
char buf[64];
u8 sw;
struct cpu_type *cpu = gd->arch.cpu;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
- unsigned int i;
static const char *const freq[] = {"100", "125", "156.25", "161.13",
"122.88", "122.88", "122.88"};
int clock;
@@ -61,19 +61,6 @@
/* the timestamp string contains "\n" at the end */
printf(" on %s", qixis_read_time(buf));
- /* Display the RCW, so that no one gets confused as to what RCW
- * we're actually using for this boot.
- */
- puts("Reset Configuration Word (RCW):");
- for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
- u32 rcw = in_be32(&gur->rcwsr[i]);
-
- if ((i % 4) == 0)
- printf("\n %08x:", i * 4);
- printf(" %08x", rcw);
- }
- puts("\n");
-
/*
* Display the actual SERDES reference clocks as configured by the
* dip switches on the board. Note that the SWx registers could
@@ -252,6 +239,106 @@
return 0;
}
+int config_serdes1_refclks(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ serdes_corenet_t *srds_regs =
+ (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ u32 serdes1_prtcl, lane;
+ unsigned int flag_sgmii_prtcl = 0;
+ int ret, i;
+
+ serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ if (!serdes1_prtcl) {
+ printf("SERDES1 is not enabled\n");
+ return -1;
+ }
+ serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+ debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
+
+ /* Clear SRDS_RSTCTL_RST bit for both PLLs before changing refclks
+ */
+ for (i = 0; i < PLL_NUM; i++)
+ clrbits_be32(&srds_regs->bank[i].rstctl, SRDS_RSTCTL_RST);
+ /* Reconfigure IDT idt8t49n222a device for CPRI to work
+ * For this SerDes1's Refclk1 and refclk2 need to be set
+ * to 122.88MHz
+ */
+ switch (serdes1_prtcl) {
+ case 0x2A:
+ case 0x2C:
+ case 0x2D:
+ case 0x2E:
+ debug("Configuring idt8t49n222a for CPRI SerDes clks:"
+ " for srds_prctl:%x\n", serdes1_prtcl);
+ ret = select_i2c_ch_pca(I2C_CH_IDT);
+ if (!ret) {
+ ret = set_serdes_refclk(IDT_SERDES1_ADDRESS, 1,
+ SERDES_REFCLK_122_88,
+ SERDES_REFCLK_122_88, 0);
+ if (ret) {
+ printf("IDT8T49N222A configuration failed.\n");
+ return ret;
+ } else
+ printf("IDT8T49N222A configured.\n");
+ } else {
+ return ret;
+ }
+ select_i2c_ch_pca(I2C_CH_DEFAULT);
+
+ /* Change SerDes1's Refclk1 to 125MHz for on board
+ * SGMIIs to work
+ */
+ for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = serdes_get_prtcl
+ (0, serdes1_prtcl, lane);
+ switch (lane_prtcl) {
+ case SGMII_FM1_DTSEC1:
+ case SGMII_FM1_DTSEC2:
+ case SGMII_FM1_DTSEC3:
+ case SGMII_FM1_DTSEC4:
+ case SGMII_FM1_DTSEC5:
+ case SGMII_FM1_DTSEC6:
+ flag_sgmii_prtcl++;
+ break;
+ default:
+ break;
+ }
+ }
+
+ if (flag_sgmii_prtcl)
+ QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
+
+ /* Steps For SerDes PLLs reset and reconfiguration after
+ * changing SerDes's refclks
+ */
+ for (i = 0; i < PLL_NUM; i++) {
+ debug("For PLL%d reset and reconfiguration after"
+ " changing refclks\n", i+1);
+ clrbits_be32(&srds_regs->bank[i].rstctl,
+ SRDS_RSTCTL_SDRST_B);
+ udelay(10);
+ clrbits_be32(&srds_regs->bank[i].rstctl,
+ (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
+ udelay(10);
+ setbits_be32(&srds_regs->bank[i].rstctl,
+ SRDS_RSTCTL_RST);
+ setbits_be32(&srds_regs->bank[i].rstctl,
+ (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
+ | SRDS_RSTCTL_SDRST_B));
+ }
+ break;
+ default:
+ printf("WARNING:IDT8T49N222A configuration not"
+ " supported for:%x SerDes1 Protocol.\n",
+ serdes1_prtcl);
+ return -1;
+ }
+
+ return 0;
+}
+
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
@@ -277,6 +364,16 @@
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals();
#endif
+ /* SerDes1 refclks need to be set again, as default clks
+ * are not suitable for CPRI and onboard SGMIIs to work
+ * simultaneously.
+ * This function will set SerDes1's Refclk1 and refclk2
+ * as per SerDes1 protocols
+ */
+ if (config_serdes1_refclks())
+ printf("SerDes1 Refclks couldn't set properly.\n");
+ else
+ printf("SerDes1 Refclks have been set.\n");
/* Configure VSC3316 and VSC3308 crossbar switches */
if (configure_vsc3316_3308())
diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c
index 19ca66e..dc4ef80 100644
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -201,8 +201,6 @@
debug("Setting phy addresses for FM1_DTSEC5: %x and"
"FM1_DTSEC6: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
- /* Fixing Serdes clock by programming FPGA register */
- QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
fm_info_set_phy_address(FM1_DTSEC5,
CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6,
diff --git a/board/freescale/bsc9131rdb/ddr.c b/board/freescale/bsc9131rdb/ddr.c
index a4161ad..c82fe0a 100644
--- a/board/freescale/bsc9131rdb/ddr.c
+++ b/board/freescale/bsc9131rdb/ddr.c
@@ -87,7 +87,7 @@
}
ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
LAW_TRGT_IF_DDR_1) < 0) {
diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c
index 4574894..a895e4e 100644
--- a/board/freescale/bsc9132qds/bsc9132qds.c
+++ b/board/freescale/bsc9132qds/bsc9132qds.c
@@ -125,6 +125,27 @@
}
}
+/* Configure DSP DDR controller */
+void dsp_ddr_configure(void)
+{
+ /*
+ *There are separate DDR-controllers for DSP and PowerPC side DDR.
+ *copy the ddr controller settings from PowerPC side DDR controller
+ *to the DSP DDR controller as connected DDR memories are similar.
+ */
+ ccsr_ddr_t __iomem *pa_ddr =
+ (ccsr_ddr_t __iomem *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ ccsr_ddr_t temp_ddr;
+ ccsr_ddr_t __iomem *dsp_ddr =
+ (ccsr_ddr_t __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
+
+ memcpy(&temp_ddr, pa_ddr, sizeof(ccsr_ddr_t));
+ temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS;
+ temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN;
+ memcpy(dsp_ddr, &temp_ddr, sizeof(ccsr_ddr_t));
+ dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN;
+}
+
int board_early_init_r(void)
{
#ifndef CONFIG_SYS_NO_FLASH
@@ -153,6 +174,7 @@
0, flash_esel+1, BOOKE_PAGESZ_64M, 1);
#endif
board_config_serdes_mux();
+ dsp_ddr_configure();
return 0;
}
diff --git a/board/freescale/bsc9132qds/ddr.c b/board/freescale/bsc9132qds/ddr.c
index 05bea8a..fdea193 100644
--- a/board/freescale/bsc9132qds/ddr.c
+++ b/board/freescale/bsc9132qds/ddr.c
@@ -109,7 +109,7 @@
strmhz(buf, ddr_freq));
ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
LAW_TRGT_IF_DDR_1) < 0) {
diff --git a/board/freescale/bsc9132qds/law.c b/board/freescale/bsc9132qds/law.c
index fed2edf..e10de9a 100644
--- a/board/freescale/bsc9132qds/law.c
+++ b/board/freescale/bsc9132qds/law.c
@@ -16,6 +16,14 @@
#ifdef CONFIG_SYS_FPGA_BASE_PHYS
SET_LAW(CONFIG_SYS_FPGA_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
#endif
+ SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M,
+ LAW_TRGT_IF_DSP_CCSR),
+ SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_32M,
+ LAW_TRGT_IF_OCN_DSP),
+ SET_LAW(CONFIG_SYS_FSL_DSP_M3_RAM_ADDR, LAW_SIZE_32K,
+ LAW_TRGT_IF_CLASS_DSP),
+ SET_LAW(CONFIG_SYS_FSL_DSP_DDR_ADDR, LAW_SIZE_1G,
+ LAW_TRGT_IF_CLASS_DSP)
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/bsc9132qds/tlb.c b/board/freescale/bsc9132qds/tlb.c
index 6d82353..02655e9 100644
--- a/board/freescale/bsc9132qds/tlb.c
+++ b/board/freescale/bsc9132qds/tlb.c
@@ -41,6 +41,11 @@
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
+ /* CCSRBAR (DSP) */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR,
+ CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, MAS3_SW|MAS3_SR,
+ MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_1M, 1),
+
#ifndef CONFIG_SPL_BUILD
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
diff --git a/board/freescale/c29xpcie/Makefile b/board/freescale/c29xpcie/Makefile
new file mode 100644
index 0000000..ab8eb8f
--- /dev/null
+++ b/board/freescale/c29xpcie/Makefile
@@ -0,0 +1,30 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+COBJS-y += cpld.o
+COBJS-y += ddr.o
+COBJS-y += law.o
+COBJS-y += tlb.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c
new file mode 100644
index 0000000..48c4b30
--- /dev/null
+++ b/board/freescale/c29xpcie/c29xpcie.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <pci.h>
+#include <asm/fsl_ifc.h>
+#include <asm/fsl_pci.h>
+
+#include "cpld.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ struct cpu_type *cpu = gd->arch.cpu;
+ struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+ printf("Board: %sPCIe, ", cpu->name);
+ printf("CPLD Ver: 0x%02x\n", in_8(&cpld_data->cpldver));
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
+
+ /* Clock configuration to access CPLD using IFC(GPCM) */
+ setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ const unsigned long flashbase = CONFIG_SYS_FLASH_BASE;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_64M, 1);
+
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+#endif /* ifdef CONFIG_PCI */
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+ struct fsl_pq_mdio_info mdio_info;
+ struct tsec_info_struct tsec_info[2];
+ int num = 0;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ num++;
+#endif
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ num++;
+#endif
+ if (!num) {
+ printf("No TSECs initialized\n");
+ return 0;
+ }
+
+ /* Register 1G MDIO bus */
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+
+ fsl_pq_mdio_init(bis, &mdio_info);
+
+ tsec_eth_init(bis, tsec_info, num);
+
+ return pci_eth_init(bis);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void fdt_del_sec(void *blob, int offset)
+{
+ int nodeoff = 0;
+
+ while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0",
+ CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET
+ + offset * 0x20000)) >= 0) {
+ fdt_del_node(blob, nodeoff);
+ offset++;
+ }
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+ struct cpu_type *cpu;
+
+ cpu = gd->arch.cpu;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+#if defined(CONFIG_PCI)
+ FT_FSL_PCI_SETUP;
+#endif
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+ if (cpu->soc_ver == SVR_C291)
+ fdt_del_sec(blob, 1);
+ else if (cpu->soc_ver == SVR_C292)
+ fdt_del_sec(blob, 2);
+}
+#endif
diff --git a/board/freescale/c29xpcie/cpld.c b/board/freescale/c29xpcie/cpld.c
new file mode 100644
index 0000000..5cbccff
--- /dev/null
+++ b/board/freescale/c29xpcie/cpld.c
@@ -0,0 +1,131 @@
+/**
+ * Copyright 2013 Freescale Semiconductor
+ * Author: Mingkai Hu <Mingkai.hu@freescale.com>
+ * Po Liu <Po.Liu@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This file provides support for the board-specific CPLD used on some Freescale
+ * reference boards.
+ *
+ * The following macros need to be defined:
+ *
+ * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the
+ * CPLD register map
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#include "cpld.h"
+/**
+ * Set the boot bank to the alternate bank
+ */
+void cpld_set_altbank(u8 banksel)
+{
+ struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+ u8 reg11;
+
+ reg11 = in_8(&cpld_data->flhcsr);
+
+ switch (banksel) {
+ case 1:
+ out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
+ | CPLD_BANKSEL_EN | CPLD_SELECT_BANK1);
+ break;
+ case 2:
+ out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
+ | CPLD_BANKSEL_EN | CPLD_SELECT_BANK2);
+ break;
+ case 3:
+ out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
+ | CPLD_BANKSEL_EN | CPLD_SELECT_BANK3);
+ break;
+ case 4:
+ out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
+ | CPLD_BANKSEL_EN | CPLD_SELECT_BANK4);
+ break;
+ default:
+ printf("Invalid value! [1-4]\n");
+ return;
+ }
+
+ udelay(100);
+ do_reset(NULL, 0, 0, NULL);
+}
+
+/**
+ * Set the boot bank to the default bank
+ */
+void cpld_set_defbank(void)
+{
+ cpld_set_altbank(4);
+}
+
+#ifdef DEBUG
+static void cpld_dump_regs(void)
+{
+ struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+ printf("chipid1 = 0x%02x\n", in_8(&cpld_data->chipid1));
+ printf("chipid2 = 0x%02x\n", in_8(&cpld_data->chipid2));
+ printf("hwver = 0x%02x\n", in_8(&cpld_data->hwver));
+ printf("cpldver = 0x%02x\n", in_8(&cpld_data->cpldver));
+ printf("rstcon = 0x%02x\n", in_8(&cpld_data->rstcon));
+ printf("flhcsr = 0x%02x\n", in_8(&cpld_data->flhcsr));
+ printf("wdcsr = 0x%02x\n", in_8(&cpld_data->wdcsr));
+ printf("wdkick = 0x%02x\n", in_8(&cpld_data->wdkick));
+ printf("fancsr = 0x%02x\n", in_8(&cpld_data->fancsr));
+ printf("ledcsr = 0x%02x\n", in_8(&cpld_data->ledcsr));
+ printf("misc = 0x%02x\n", in_8(&cpld_data->misccsr));
+ printf("bootor = 0x%02x\n", in_8(&cpld_data->bootor));
+ printf("bootcfg1 = 0x%02x\n", in_8(&cpld_data->bootcfg1));
+ printf("bootcfg2 = 0x%02x\n", in_8(&cpld_data->bootcfg2));
+ printf("bootcfg3 = 0x%02x\n", in_8(&cpld_data->bootcfg3));
+ printf("bootcfg4 = 0x%02x\n", in_8(&cpld_data->bootcfg4));
+ putc('\n');
+}
+#endif
+
+int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rc = 0;
+ unsigned char value;
+
+ if (argc <= 1)
+ return cmd_usage(cmdtp);
+
+ if (strcmp(argv[1], "reset") == 0) {
+ if (!strcmp(argv[2], "altbank") && argv[3]) {
+ value = (u8)simple_strtoul(argv[3], NULL, 16);
+ cpld_set_altbank(value);
+ } else if (!argv[2])
+ cpld_set_defbank();
+ else
+ cmd_usage(cmdtp);
+#ifdef DEBUG
+ } else if (strcmp(argv[1], "dump") == 0) {
+ cpld_dump_regs();
+#endif
+ } else
+ rc = cmd_usage(cmdtp);
+
+ return rc;
+}
+
+U_BOOT_CMD(
+ cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd,
+ "Reset the board using the CPLD sequencer",
+ "reset - hard reset to default bank 4\n"
+ "cpld_cmd reset altbank [bank]- reset to alternate bank\n"
+ " - [bank] bank value select 1-4\n"
+ " - bank 1 on the flash 0x0000000~0x0ffffff\n"
+ " - bank 2 on the flash 0x1000000~0x1ffffff\n"
+ " - bank 3 on the flash 0x2000000~0x2ffffff\n"
+ " - bank 4 on the flash 0x3000000~0x3ffffff\n"
+#ifdef DEBUG
+ "cpld_cmd dump - display the CPLD registers\n"
+#endif
+ );
diff --git a/board/freescale/c29xpcie/cpld.h b/board/freescale/c29xpcie/cpld.h
new file mode 100644
index 0000000..20862a3
--- /dev/null
+++ b/board/freescale/c29xpcie/cpld.h
@@ -0,0 +1,40 @@
+/**
+ * Copyright 2013 Freescale Semiconductor
+ * Author: Mingkai Hu <Mingkai.Hu@freescale.com>
+ * Po Liu <Po.Liu@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This file provides support for the ngPIXIS, a board-specific FPGA used on
+ * some Freescale reference boards.
+ */
+
+/*
+ * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
+ */
+struct cpld_data {
+ u8 chipid1; /* 0x0 - CPLD Chip ID1 Register */
+ u8 chipid2; /* 0x1 - CPLD Chip ID2 Register */
+ u8 hwver; /* 0x2 - Hardware Version Register */
+ u8 cpldver; /* 0x3 - Software Version Register */
+ u8 res[12];
+ u8 rstcon; /* 0x10 - Reset control register */
+ u8 flhcsr; /* 0x11 - Flash control and status Register */
+ u8 wdcsr; /* 0x12 - Watchdog control and status Register */
+ u8 wdkick; /* 0x13 - Watchdog kick Register */
+ u8 fancsr; /* 0x14 - Fan control and status Register */
+ u8 ledcsr; /* 0x15 - LED control and status Register */
+ u8 misccsr; /* 0x16 - Misc control and status Register */
+ u8 bootor; /* 0x17 - Boot configure override Register */
+ u8 bootcfg1; /* 0x18 - Boot configure 1 Register */
+ u8 bootcfg2; /* 0x19 - Boot configure 2 Register */
+ u8 bootcfg3; /* 0x1a - Boot configure 3 Register */
+ u8 bootcfg4; /* 0x1b - Boot configure 4 Register */
+};
+
+#define CPLD_BANKSEL_EN 0x02
+#define CPLD_BANKSEL_MASK 0x3f
+#define CPLD_SELECT_BANK1 0xc0
+#define CPLD_SELECT_BANK2 0x80
+#define CPLD_SELECT_BANK3 0x40
+#define CPLD_SELECT_BANK4 0x00
diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c
new file mode 100644
index 0000000..b017cfd
--- /dev/null
+++ b/board/freescale/c29xpcie/ddr.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+/*
+ * Micron MT41J128M16HA-15E
+ * */
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 1,
+ .rank_density = 536870912u,
+ .capacity = 536870912u,
+ .primary_sdram_width = 32,
+ .ec_sdram_width = 8,
+ .registered_dimm = 0,
+ .mirrored_dimm = 0,
+ .n_row_addr = 14,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 2,
+ .burst_lengths_bitmask = 0x0c,
+
+ .tCKmin_X_ps = 1650,
+ .caslat_X = 0x7e << 4, /* 5,6,7,8,9,10 */
+ .tAA_ps = 14050,
+ .tWR_ps = 15000,
+ .tRCD_ps = 13500,
+ .tRRD_ps = 75000,
+ .tRP_ps = 13500,
+ .tRAS_ps = 40000,
+ .tRC_ps = 49500,
+ .tRFC_ps = 160000,
+ .tWTR_ps = 75000,
+ .tRTP_ps = 75000,
+ .refresh_rate_ps = 7800000,
+ .tFAW_ps = 30000,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+ unsigned int controller_number,
+ unsigned int dimm_number)
+{
+ const char dimm_model[] = "Fixed DDR on board";
+
+ if ((controller_number == 0) && (dimm_number == 0)) {
+ memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+ }
+
+ return 0;
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ int i;
+ popts->clk_adjust = 2;
+ popts->cpo_override = 0x1f;
+ popts->write_data_delay = 4;
+ popts->half_strength_driver_enable = 1;
+ popts->bstopre = 0x3cf;
+ popts->quad_rank_present = 1;
+ popts->rtt_override = 1;
+ popts->rtt_override_value = 1;
+ popts->dynamic_power = 1;
+ /* Write leveling override */
+ popts->wrlvl_en = 1;
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+ popts->wrlvl_start = 0x4;
+ popts->trwt_override = 1;
+ popts->trwt = 0;
+
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
+ popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
+ }
+}
diff --git a/board/freescale/c29xpcie/law.c b/board/freescale/c29xpcie/law.c
new file mode 100644
index 0000000..cd8fc21
--- /dev/null
+++ b/board/freescale/c29xpcie/law.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
+ SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_16K, LAW_TRGT_IF_IFC),
+ SET_LAW(CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, LAW_SIZE_512K,
+ LAW_TRGT_IF_PLATFORM_SRAM),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c
new file mode 100644
index 0000000..ddd1ef8
--- /dev/null
+++ b/board/freescale/c29xpcie/tlb.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_64M, 1),
+
+#ifdef CONFIG_PCI
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_256K, 1),
+#endif
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_4K, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_16K, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
+ CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE + 0x40000,
+ CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS + 0x40000,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 7, BOOKE_PAGESZ_256K, 1),
+
+#ifdef CONFIG_SYS_RAMBOOT
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
+ CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 8, BOOKE_PAGESZ_256M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+ CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 9, BOOKE_PAGESZ_256M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index d451f6f..457d1ad 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -54,6 +54,7 @@
COBJS-$(CONFIG_P5020DS) += ics307_clk.o
COBJS-$(CONFIG_P5040DS) += ics307_clk.o
COBJS-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o
+COBJS-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o
# deal with common files for P-series corenet based devices
SUBLIB-$(CONFIG_P2041RDB) += p_corenet/libp_corenet.o
diff --git a/board/freescale/common/idt8t49n222a_serdes_clk.c b/board/freescale/common/idt8t49n222a_serdes_clk.c
new file mode 100644
index 0000000..d347162
--- /dev/null
+++ b/board/freescale/common/idt8t49n222a_serdes_clk.c
@@ -0,0 +1,207 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ * Author: Shaveta Leekha <shaveta@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "idt8t49n222a_serdes_clk.h"
+
+#define DEVICE_ID_REG 0x00
+
+static int check_pll_status(u8 idt_addr)
+{
+ u8 val = 0;
+ int ret;
+
+ ret = i2c_read(idt_addr, 0x17, 1, &val, 1);
+ if (ret < 0) {
+ printf("IDT:0x%x could not read status register from device.\n",
+ idt_addr);
+ return ret;
+ }
+
+ if (val & 0x04) {
+ debug("idt8t49n222a PLL is LOCKED: %x\n", val);
+ } else {
+ printf("idt8t49n222a PLL is not LOCKED: %x\n", val);
+ return -1;
+ }
+
+ return 0;
+}
+
+int set_serdes_refclk(u8 idt_addr, u8 serdes_num,
+ enum serdes_refclk refclk1,
+ enum serdes_refclk refclk2, u8 feedback)
+{
+ u8 dev_id = 0;
+ int i, ret;
+
+ debug("IDT:Configuring idt8t49n222a device at I2C address: 0x%2x\n",
+ idt_addr);
+
+ ret = i2c_read(idt_addr, DEVICE_ID_REG, 1, &dev_id, 1);
+ if (ret < 0) {
+ debug("IDT:0x%x could not read DEV_ID from device.\n",
+ idt_addr);
+ return ret;
+ }
+
+ if ((dev_id != 0x00) && (dev_id != 0x24) && (dev_id != 0x2a)) {
+ debug("IDT: device at address 0x%x is not idt8t49n222a.\n",
+ idt_addr);
+ }
+
+ if (serdes_num != 1 && serdes_num != 2) {
+ debug("serdes_num should be 1 for SerDes1 and"
+ " 2 for SerDes2.\n");
+ return -1;
+ }
+
+ if ((refclk1 == SERDES_REFCLK_122_88 && refclk2 != SERDES_REFCLK_122_88)
+ || (refclk1 != SERDES_REFCLK_122_88
+ && refclk2 == SERDES_REFCLK_122_88)) {
+ debug("Only one refclk at 122.88MHz is not supported."
+ " Please set both refclk1 & refclk2 to 122.88MHz"
+ " or both not to 122.88MHz.\n");
+ return -1;
+ }
+
+ if (refclk1 != SERDES_REFCLK_100 && refclk1 != SERDES_REFCLK_122_88
+ && refclk1 != SERDES_REFCLK_125
+ && refclk1 != SERDES_REFCLK_156_25) {
+ debug("refclk1 should be 100MHZ, 122.88MHz, 125MHz"
+ " or 156.25MHz.\n");
+ return -1;
+ }
+
+ if (refclk2 != SERDES_REFCLK_100 && refclk2 != SERDES_REFCLK_122_88
+ && refclk2 != SERDES_REFCLK_125
+ && refclk2 != SERDES_REFCLK_156_25) {
+ debug("refclk2 should be 100MHZ, 122.88MHz, 125MHz"
+ " or 156.25MHz.\n");
+ return -1;
+ }
+
+ if (feedback != 0 && feedback != 1) {
+ debug("valid values for feedback are 0(default) or 1.\n");
+ return -1;
+ }
+
+ /* Configuring IDT for output refclks as
+ * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
+ */
+ if (refclk1 == SERDES_REFCLK_122_88 &&
+ refclk2 == SERDES_REFCLK_122_88) {
+ printf("Setting refclk1:122.88 and refclk2:122.88\n");
+ for (i = 0; i < NUM_IDT_REGS; i++)
+ i2c_reg_write(idt_addr, idt_conf_122_88[i][0],
+ idt_conf_122_88[i][1]);
+
+ if (feedback) {
+ for (i = 0; i < NUM_IDT_REGS_FEEDBACK; i++)
+ i2c_reg_write(idt_addr,
+ idt_conf_122_88_feedback[i][0],
+ idt_conf_122_88_feedback[i][1]);
+ }
+ }
+
+ if (refclk1 != SERDES_REFCLK_122_88 &&
+ refclk2 != SERDES_REFCLK_122_88) {
+ for (i = 0; i < NUM_IDT_REGS; i++)
+ i2c_reg_write(idt_addr, idt_conf_not_122_88[i][0],
+ idt_conf_not_122_88[i][1]);
+ }
+
+ /* Configuring IDT for output refclks as
+ * Refclk1 = 100MHz Refclk2 = 125MHz
+ */
+ if (refclk1 == SERDES_REFCLK_100 && refclk2 == SERDES_REFCLK_125) {
+ printf("Setting refclk1:100 and refclk2:125\n");
+ i2c_reg_write(idt_addr, 0x11, 0x10);
+ }
+
+ /* Configuring IDT for output refclks as
+ * Refclk1 = 125MHz Refclk2 = 125MHz
+ */
+ if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_125) {
+ printf("Setting refclk1:125 and refclk2:125\n");
+ i2c_reg_write(idt_addr, 0x10, 0x10);
+ i2c_reg_write(idt_addr, 0x11, 0x10);
+ }
+
+ /* Configuring IDT for output refclks as
+ * Refclk1 = 125MHz Refclk2 = 100MHz
+ */
+ if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_100) {
+ printf("Setting refclk1:125 and refclk2:100\n");
+ i2c_reg_write(idt_addr, 0x10, 0x10);
+ }
+
+ /* Configuring IDT for output refclks as
+ * Refclk1 = 156.25MHz Refclk2 = 156.25MHz
+ */
+ if (refclk1 == SERDES_REFCLK_156_25 &&
+ refclk2 == SERDES_REFCLK_156_25) {
+ printf("Setting refclk1:156.25 and refclk2:156.25\n");
+ for (i = 0; i < NUM_IDT_REGS_156_25; i++)
+ i2c_reg_write(idt_addr, idt_conf_156_25[i][0],
+ idt_conf_156_25[i][1]);
+ }
+
+ /* Configuring IDT for output refclks as
+ * Refclk1 = 100MHz Refclk2 = 156.25MHz
+ */
+ if (refclk1 == SERDES_REFCLK_100 &&
+ refclk2 == SERDES_REFCLK_156_25) {
+ printf("Setting refclk1:100 and refclk2:156.25\n");
+ for (i = 0; i < NUM_IDT_REGS_156_25; i++)
+ i2c_reg_write(idt_addr, idt_conf_100_156_25[i][0],
+ idt_conf_100_156_25[i][1]);
+ }
+
+ /* Configuring IDT for output refclks as
+ * Refclk1 = 125MHz Refclk2 = 156.25MHz
+ */
+ if (refclk1 == SERDES_REFCLK_125 &&
+ refclk2 == SERDES_REFCLK_156_25) {
+ printf("Setting refclk1:125 and refclk2:156.25\n");
+ for (i = 0; i < NUM_IDT_REGS_156_25; i++)
+ i2c_reg_write(idt_addr, idt_conf_125_156_25[i][0],
+ idt_conf_125_156_25[i][1]);
+ }
+
+ /* Configuring IDT for output refclks as
+ * Refclk1 = 156.25MHz Refclk2 = 100MHz
+ */
+ if (refclk1 == SERDES_REFCLK_156_25 &&
+ refclk2 == SERDES_REFCLK_100) {
+ printf("Setting refclk1:156.25 and refclk2:100\n");
+ for (i = 0; i < NUM_IDT_REGS_156_25; i++)
+ i2c_reg_write(idt_addr, idt_conf_156_25_100[i][0],
+ idt_conf_156_25_100[i][1]);
+ }
+
+ /* Configuring IDT for output refclks as
+ * Refclk1 = 156.25MHz Refclk2 = 125MHz
+ */
+ if (refclk1 == SERDES_REFCLK_156_25 &&
+ refclk2 == SERDES_REFCLK_125) {
+ printf("Setting refclk1:156.25 and refclk2:125\n");
+ for (i = 0; i < NUM_IDT_REGS_156_25; i++)
+ i2c_reg_write(idt_addr, idt_conf_156_25_125[i][0],
+ idt_conf_156_25_125[i][1]);
+ }
+
+ /* waiting for maximum of 1 second if PLL doesn'r get locked
+ * initially. then check the status again.
+ */
+ if (check_pll_status(idt_addr)) {
+ mdelay(1000);
+ if (check_pll_status(idt_addr))
+ return -1;
+ }
+
+ return 0;
+}
diff --git a/board/freescale/common/idt8t49n222a_serdes_clk.h b/board/freescale/common/idt8t49n222a_serdes_clk.h
new file mode 100644
index 0000000..787bdd9
--- /dev/null
+++ b/board/freescale/common/idt8t49n222a_serdes_clk.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ * Author: Shaveta Leekha <shaveta@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __IDT8T49N222A_SERDES_CLK_H_
+#define __IDT8T49N222A_SERDES_CLK_H_ 1
+
+#include <common.h>
+#include <i2c.h>
+#include "qixis.h"
+#include "../b4860qds/b4860qds_qixis.h"
+#include <errno.h>
+
+#define NUM_IDT_REGS 23
+#define NUM_IDT_REGS_FEEDBACK 12
+#define NUM_IDT_REGS_156_25 11
+
+/* CLK */
+enum serdes_refclk {
+ SERDES_REFCLK_100, /* refclk 100Mhz */
+ SERDES_REFCLK_122_88, /* refclk 122.88Mhz */
+ SERDES_REFCLK_125, /* refclk 125Mhz */
+ SERDES_REFCLK_156_25, /* refclk 156.25Mhz */
+ SERDES_REFCLK_NONE = -1,
+};
+
+/* configuration values for IDT registers for Output Refclks:
+ * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
+ */
+static const u8 idt_conf_122_88[23][2] = { {0x00, 0x3C}, {0x01, 0x00},
+ {0x02, 0x9F}, {0x03, 0x00}, {0x04, 0x0B}, {0x05, 0x00},
+ {0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00},
+ {0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00},
+ {0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x12}, {0x11, 0x12},
+ {0x12, 0xB9}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08},
+ {0x16, 0xA0} };
+
+
+/* configuration values for IDT registers for Output Refclks:
+ * Refclk1 not equal to 122.88MHz Refclk2 not equal to 122.88MHz
+ */
+static const u8 idt_conf_not_122_88[23][2] = { {0x00, 0x00}, {0x01, 0x00},
+ {0x02, 0x00}, {0x03, 0x00}, {0x04, 0x0A}, {0x05, 0x00},
+ {0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00},
+ {0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00},
+ {0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x14}, {0x11, 0x14},
+ {0x12, 0x35}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08},
+ {0x16, 0xA0} };
+
+/* Reconfiguration values for some of IDT registers for
+ * Output Refclks:
+ * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
+ * and with feedback as 1
+ */
+static const u8 idt_conf_122_88_feedback[12][2] = { {0x00, 0x50}, {0x02, 0xD7},
+ {0x04, 0x89}, {0x06, 0xC3}, {0x08, 0xC0}, {0x0A, 0x07},
+ {0x0C, 0x80}, {0x10, 0x10}, {0x11, 0x10}, {0x12, 0x1B},
+ {0x14, 0x00}, {0x15, 0xE8} };
+
+/* configuration values for IDT registers for Output Refclks:
+ * Refclk1 : 156.25MHz Refclk2 : 156.25MHz
+ */
+static const u8 idt_conf_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
+ {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
+ {0x10, 0x10}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
+ {0x15, 0xE8} };
+
+/* configuration values for IDT registers for Output Refclks:
+ * Refclk1 : 100MHz Refclk2 : 156.25MHz
+ */
+static const u8 idt_conf_100_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
+ {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
+ {0x10, 0x19}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
+ {0x15, 0xE8} };
+
+/* configuration values for IDT registers for Output Refclks:
+ * Refclk1 : 125MHz Refclk2 : 156.25MHz
+ */
+static const u8 idt_conf_125_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
+ {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
+ {0x10, 0x14}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
+ {0x15, 0xE8} };
+
+/* configuration values for IDT registers for Output Refclks:
+ * Refclk1 : 156.25MHz Refclk2 : 100MHz
+ */
+static const u8 idt_conf_156_25_100[11][2] = { {0x04, 0x19}, {0x06, 0x03},
+ {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
+ {0x10, 0x10}, {0x11, 0x19}, {0x12, 0xB5}, {0x13, 0x3C},
+ {0x15, 0xE8} };
+
+/* configuration values for IDT registers for Output Refclks:
+ * Refclk1 : 156.25MHz Refclk2 : 125MHz
+ */
+static const u8 idt_conf_156_25_125[11][2] = { {0x04, 0x19}, {0x06, 0x03},
+ {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
+ {0x10, 0x10}, {0x11, 0x14}, {0x12, 0xB5}, {0x13, 0x3C},
+ {0x15, 0xE8} };
+
+int set_serdes_refclk(u8 idt_addr, u8 serdes_num,
+ enum serdes_refclk refclk1,
+ enum serdes_refclk refclk2, u8 feedback);
+
+#endif /*__IDT8T49N222A_SERDES_CLK_H_ */
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 40ce6b0..a49e300 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -107,6 +107,26 @@
return buf;
}
+#ifdef QIXIS_RST_FORCE_MEM
+void board_assert_mem_reset(void)
+{
+ u8 rst;
+
+ rst = QIXIS_READ(rst_frc[0]);
+ if (!(rst & QIXIS_RST_FORCE_MEM))
+ QIXIS_WRITE(rst_frc[0], rst | QIXIS_RST_FORCE_MEM);
+}
+
+void board_deassert_mem_reset(void)
+{
+ u8 rst;
+
+ rst = QIXIS_READ(rst_frc[0]);
+ if (rst & QIXIS_RST_FORCE_MEM)
+ QIXIS_WRITE(rst_frc[0], rst & ~QIXIS_RST_FORCE_MEM);
+}
+#endif
+
void qixis_reset(void)
{
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c
index fffb0c8..60e2100 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -27,8 +27,10 @@
{
u8 sw;
struct cpu_type *cpu = gd->arch.cpu;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) || \
+ defined(CONFIG_P5040DS)
unsigned int i;
+#endif
static const char * const freq[] = {"100", "125", "156.25", "212.5" };
printf("Board: %sDS, ", cpu->name);
@@ -47,19 +49,6 @@
else
printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
- /* Display the RCW, so that no one gets confused as to what RCW
- * we're actually using for this boot.
- */
- puts("Reset Configuration Word (RCW):");
- for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
- u32 rcw = in_be32(&gur->rcwsr[i]);
-
- if ((i % 4) == 0)
- printf("\n %08x:", i * 4);
- printf(" %08x", rcw);
- }
- puts("\n");
-
/* Display the actual SERDES reference clocks as configured by the
* dip switches on the board. Note that the SWx registers could
* technically be set to force the reference clocks to match the
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
index da284cd..517e87f 100644
--- a/board/freescale/corenet_ds/ddr.c
+++ b/board/freescale/corenet_ds/ddr.c
@@ -56,14 +56,14 @@
ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
memcpy(&ddr_cfg_regs,
fixed_ddr_parm_1[i].ddr_settings,
sizeof(ddr_cfg_regs));
ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1);
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1, 0);
#endif
/*
diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c
index aa8bada..681f052 100644
--- a/board/freescale/p1010rdb/ddr.c
+++ b/board/freescale/p1010rdb/ddr.c
@@ -139,7 +139,7 @@
}
ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
LAW_TRGT_IF_DDR_1) < 0) {
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index 0038077..5bee22e 100644
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -220,7 +220,7 @@
ddr_cfg_regs.cs[0].bnds = 0x0000001F;
}
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1);
return ddr_size;
diff --git a/board/freescale/p1_p2_rdb_pc/README b/board/freescale/p1_p2_rdb_pc/README
index 4437731..f4cc43f 100644
--- a/board/freescale/p1_p2_rdb_pc/README
+++ b/board/freescale/p1_p2_rdb_pc/README
@@ -3,6 +3,7 @@
P1_P2_RDB_PC represents a set of boards including
P1020MSBG-PC
P1020RDB-PC
+ P1020RDB-PD
P1020UTM-PC
P1021RDB-PC
P1024RDB
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index 9355536..5c51845 100644
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -80,7 +80,7 @@
.refresh_rate_ps = 7800000,
.tFAW_ps = 30000,
};
-#elif defined(CONFIG_P1020MBG)
+#elif (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
/* Micron MT41J512M8_187E */
dimm_params_t ddr_raw_timing = {
.n_ranks = 2,
@@ -111,7 +111,7 @@
.refresh_rate_ps = 7800000,
.tFAW_ps = 37500,
};
-#elif defined(CONFIG_P1020RDB)
+#elif defined(CONFIG_P1020RDB_PC)
/*
* Samsung K4B2G0846C-HCF8
* The following timing are for "downshift"
@@ -251,7 +251,7 @@
ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 93896dc..d4561c7 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -94,7 +94,7 @@
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 8, BOOKE_PAGESZ_1G, 1),
-#ifdef CONFIG_P1020MBG
+#if defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)
/* 2G DDR on P1020MBG, map the second 1G */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
diff --git a/board/freescale/p1_twr/Makefile b/board/freescale/p1_twr/Makefile
new file mode 100644
index 0000000..915b9bc
--- /dev/null
+++ b/board/freescale/p1_twr/Makefile
@@ -0,0 +1,35 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+COBJS-y += ddr.o
+COBJS-y += law.o
+COBJS-y += tlb.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/p1_twr/ddr.c b/board/freescale/p1_twr/ddr.c
new file mode 100644
index 0000000..697c0dd
--- /dev/null
+++ b/board/freescale/p1_twr/ddr.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+/* Fixed sdram init -- doesn't use serial presence detect. */
+phys_size_t fixed_sdram(void)
+{
+ sys_info_t sysinfo;
+ char buf[32];
+ size_t ddr_size;
+ fsl_ddr_cfg_regs_t ddr_cfg_regs = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
+ .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+ .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+ .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
+#endif
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
+ .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+ .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+ };
+
+ get_sys_info(&sysinfo);
+ printf("Configuring DDR for %s MT/s data rate\n",
+ strmhz(buf, sysinfo.freqDDRBus));
+
+ ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
+
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+ ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ };
+
+ return ddr_size;
+}
diff --git a/board/freescale/p1_twr/law.c b/board/freescale/p1_twr/law.c
new file mode 100644
index 0000000..e79d8a4
--- /dev/null
+++ b/board/freescale/p1_twr/law.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_SSD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC)
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1_twr/p1_twr.c b/board/freescale/p1_twr/p1_twr.c
new file mode 100644
index 0000000..ea8db6f
--- /dev/null
+++ b/board/freescale/p1_twr/p1_twr.c
@@ -0,0 +1,281 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <hwconfig.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_lbc.h>
+#include <asm/mp.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <ioports.h>
+#include <asm/fsl_serdes.h>
+#include <netdev.h>
+
+#define SYSCLK_64 64000000
+#define SYSCLK_66 66666666
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
+ unsigned int cpdat_val = 0;
+
+ /* Set-up up pin muxing based on board switch settings */
+ cpdat_val = par_io[1].cpdat;
+
+ /* Check switch setting for SYSCLK select (PB3) */
+ if (cpdat_val & 0x10000000)
+ return SYSCLK_64;
+ else
+ return SYSCLK_66;
+
+ return 0;
+}
+
+#ifdef CONFIG_QE
+
+#define PCA_IOPORT_I2C_ADDR 0x23
+#define PCA_IOPORT_OUTPUT_CMD 0x2
+#define PCA_IOPORT_CFG_CMD 0x6
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+
+#ifdef CONFIG_TWR_P1025
+ /* GPIO */
+ {1, 0, 1, 0, 0},
+ {1, 18, 1, 0, 0},
+
+ /* GPIO for switch options */
+ {1, 2, 2, 0, 0}, /* PROFIBUS_MODE_SEL */
+ {1, 3, 2, 0, 0}, /* SYS_CLK_SELECT */
+ {1, 29, 2, 0, 0}, /* LOCALBUS_QE_MUXSEL */
+ {1, 30, 2, 0, 0}, /* ETH_TDM_SEL */
+
+ /* QE_MUX_MDC */
+ {1, 19, 1, 0, 1}, /* QE_MUX_MDC */
+
+ /* QE_MUX_MDIO */
+ {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
+
+ /* UCC_1_MII */
+ {0, 23, 2, 0, 2}, /* CLK12 */
+ {0, 24, 2, 0, 1}, /* CLK9 */
+ {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
+ {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
+ {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
+ {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
+ {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
+ {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
+ {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
+ {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
+ {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
+ {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
+ {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
+ {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
+ {0, 17, 2, 0, 2}, /* ENET1_CRS */
+ {0, 16, 2, 0, 2}, /* ENET1_COL */
+
+ /* UCC_5_RMII */
+ {1, 11, 2, 0, 1}, /* CLK13 */
+ {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
+ {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
+ {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
+ {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
+ {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
+ {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
+ {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
+
+ /* TDMA - clock option is configured in OS based on board setting */
+ {1, 23, 2, 0, 2}, /* TDMA_TXD */
+ {1, 25, 2, 0, 2}, /* TDMA_RXD */
+ {1, 26, 1, 0, 2}, /* TDMA_SYNC */
+#endif
+
+ {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
+};
+#endif
+
+int board_early_init_f(void)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ setbits_be32(&gur->pmuxcr,
+ (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
+
+ /* SDHC_DAT[4:7] not exposed to pins (use as SPI) */
+ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u8 boot_status;
+
+ printf("Board: %s\n", CONFIG_BOARDNAME);
+
+ boot_status = ((gur->porbmsr) >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
+ puts("rom_loc: ");
+ if (boot_status == PORBMSR_ROMLOC_NOR)
+ puts("nor flash");
+ else if (boot_status == PORBMSR_ROMLOC_SDHC)
+ puts("sd");
+ else
+ puts("unknown");
+ puts("\n");
+
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+#endif
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
+ 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ struct fsl_pq_mdio_info mdio_info;
+ struct tsec_info_struct tsec_info[4];
+ ccsr_gur_t *gur __attribute__((unused)) =
+ (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ int num = 0;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ num++;
+#endif
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ if (is_serdes_configured(SGMII_TSEC2)) {
+ printf("eTSEC2 is in sgmii mode.\n");
+ tsec_info[num].flags |= TSEC_SGMII;
+ }
+ num++;
+#endif
+#ifdef CONFIG_TSEC3
+ SET_STD_TSEC_INFO(tsec_info[num], 3);
+ num++;
+#endif
+
+ if (!num) {
+ printf("No TSECs initialized\n");
+ return 0;
+ }
+
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+
+ fsl_pq_mdio_init(bis, &mdio_info);
+
+ tsec_eth_init(bis, tsec_info, num);
+
+#if defined(CONFIG_UEC_ETH)
+ /* QE0 and QE3 need to be exposed for UCC1
+ * and UCC5 Eth mode (in PMUXCR register).
+ * Currently QE/LBC muxed pins assumed to be
+ * LBC for U-Boot and PMUXCR updated by OS if required */
+
+ uec_standard_init(bis);
+#endif
+
+ return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_QE)
+static void fdt_board_fixup_qe_pins(void *blob)
+{
+ int node;
+
+ if (!hwconfig("qe")) {
+ /* For QE and eLBC pins multiplexing,
+ * When don't use QE function, remove
+ * qe node from dt blob.
+ */
+ node = fdt_path_offset(blob, "/qe");
+ if (node >= 0)
+ fdt_del_node(blob, node);
+ } else {
+ /* For TWR Peripheral Modules - TWR-SER2
+ * board only can support Signal Port MII,
+ * so delete one UEC node when use MII port.
+ */
+ if (hwconfig("mii"))
+ node = fdt_path_offset(blob, "/qe/ucc@2400");
+ else
+ node = fdt_path_offset(blob, "/qe/ucc@2000");
+ if (node >= 0)
+ fdt_del_node(blob, node);
+ }
+
+ return;
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+ FT_FSL_PCI_SETUP;
+
+#ifdef CONFIG_QE
+ do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
+ sizeof("okay"), 0);
+#endif
+#if defined(CONFIG_TWR_P1025)
+ fdt_board_fixup_qe_pins(blob);
+#endif
+ fdt_fixup_dr_usb(blob, bd);
+}
+#endif
diff --git a/board/freescale/p1_twr/tlb.c b/board/freescale/p1_twr/tlb.c
new file mode 100644
index 0000000..308335c
--- /dev/null
+++ b/board/freescale/p1_twr/tlb.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+ /* W**G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_64M, 1),
+
+ /* W**G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SSD_BASE, CONFIG_SYS_SSD_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_1M, 1),
+
+#ifdef CONFIG_PCI
+ /* *I*G* - PCI memory 1.5G */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI I/O effective: 192K */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256K, 1),
+#endif
+
+#endif
+
+#ifdef CONFIG_SYS_RAMBOOT
+ /* *I*G - eSDHC boot */
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 8, BOOKE_PAGESZ_1G, 1),
+#endif
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index 08d10bc..60694a6 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -28,7 +28,6 @@
{
u8 sw;
struct cpu_type *cpu = gd->arch.cpu;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
unsigned int i;
printf("Board: %sRDB, ", cpu->name);
@@ -39,20 +38,6 @@
printf("vBank: %d\n", sw & 0x1);
/*
- * Display the RCW, so that no one gets confused as to what RCW
- * we're actually using for this boot.
- */
- puts("Reset Configuration Word (RCW):");
- for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
- u32 rcw = in_be32(&gur->rcwsr[i]);
-
- if ((i % 4) == 0)
- printf("\n %08x:", i * 4);
- printf(" %08x", rcw);
- }
- puts("\n");
-
- /*
* Display the actual SERDES reference clocks as configured by the
* dip switches on the board. Note that the SWx registers could
* technically be set to force the reference clocks to match the
diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile
index 85df066..a2167b3 100644
--- a/board/freescale/t4qds/Makefile
+++ b/board/freescale/t4qds/Makefile
@@ -8,7 +8,8 @@
LIB = $(obj)lib$(BOARD).o
-COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_T4240QDS) += t4240qds.o
+COBJS-$(CONFIG_T4240EMU) += t4240emu.o
COBJS-y += ddr.o
COBJS-$(CONFIG_T4240QDS)+= eth.o
COBJS-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
index 058d625..26ac2a5 100644
--- a/board/freescale/t4qds/ddr.c
+++ b/board/freescale/t4qds/ddr.c
@@ -13,81 +13,10 @@
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
+#include "ddr.h"
DECLARE_GLOBAL_DATA_PTR;
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 rank_gb;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 wrlvl_ctl_2;
- u32 wrlvl_ctl_3;
- u32 cpo;
- u32 write_data_delay;
- u32 force_2T;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
- */
- {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
- {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
- {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
- {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
- {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
- {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
- {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
- {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
- {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
- {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
- {}
-};
-
-/*
- * The three slots have slightly different timing. The center values are good
- * for all slots. We use identical speed tables for them. In future use, if
- * DIMMs require separated tables, make more entries as needed.
- */
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
-};
-
-static const struct board_specific_parameters rdimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
- */
- {4, 1350, 0, 5, 9, 0x08070605, 0x07080805, 0xff, 2, 0},
- {4, 1666, 0, 5, 8, 0x08070605, 0x07080805, 0xff, 2, 0},
- {4, 2140, 0, 5, 8, 0x08070605, 0x07081805, 0xff, 2, 0},
- {2, 1350, 0, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff, 2, 0},
- {2, 1666, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
- {2, 2140, 0, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
- {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
- {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
- {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
- {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
- {}
-};
-
-/*
- * The three slots have slightly different timing. See comments above.
- */
-static const struct board_specific_parameters *rdimms[] = {
- rdimm0,
-};
-
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
diff --git a/board/freescale/t4qds/ddr.h b/board/freescale/t4qds/ddr.h
new file mode 100644
index 0000000..d0a0951
--- /dev/null
+++ b/board/freescale/t4qds/ddr.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+ u32 cpo;
+ u32 write_data_delay;
+ u32 force_2T;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+#ifdef CONFIG_T4240QDS
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
+ */
+ {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
+ {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
+ {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
+ {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
+ {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
+ {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
+ {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
+ {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
+ {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
+ {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
+ {}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
+ */
+ {4, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
+ {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906, 0xff, 2, 0},
+ {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
+ {2, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
+ {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
+ {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
+ {1, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
+ {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
+ {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
+ {}
+};
+
+#else /* CONFIG_T4240EMU */
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
+ */
+ {2, 2140, 0, 4, 8, 0x0, 0x0, 0xff, 2, 0},
+ {1, 2140, 0, 4, 8, 0x0, 0x0, 0xff, 2, 0},
+ {}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
+ */
+ {4, 2140, 0, 5, 8, 0x0, 0x0, 0xff, 2, 0},
+ {2, 2140, 0, 5, 8, 0x0, 0x0, 0xff, 2, 0},
+ {1, 2140, 0, 4, 8, 0x0, 0x0, 0xff, 2, 0},
+ {}
+};
+#endif /* CONFIG_T4240EMU */
+
+/*
+ * The three slots have slightly different timing. The center values are good
+ * for all slots. We use identical speed tables for them. In future use, if
+ * DIMMs require separated tables, make more entries as needed.
+ */
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+
+/*
+ * The three slots have slightly different timing. See comments above.
+ */
+static const struct board_specific_parameters *rdimms[] = {
+ rdimm0,
+};
+
+
+#endif
diff --git a/board/freescale/t4qds/law.c b/board/freescale/t4qds/law.c
index 63549df..367783b 100644
--- a/board/freescale/t4qds/law.c
+++ b/board/freescale/t4qds/law.c
@@ -19,7 +19,9 @@
#ifdef CONFIG_SYS_QMAN_MEM_PHYS
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
#endif
+#ifdef QIXIS_BASE_PHYS
SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
/* Limit DCSR to 32M to access NPC Trace Buffer */
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
diff --git a/board/freescale/t4qds/t4240emu.c b/board/freescale/t4qds/t4240emu.c
new file mode 100644
index 0000000..7a61036
--- /dev/null
+++ b/board/freescale/t4qds/t4240emu.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ struct cpu_type *cpu = gd->arch.cpu;
+
+ printf("Board: %sEMU\n", cpu->name);
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+ fdt_fixup_liodn(blob);
+ fdt_fixup_dr_usb(blob, bd);
+}
diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4240qds.c
similarity index 92%
rename from board/freescale/t4qds/t4qds.c
rename to board/freescale/t4qds/t4240qds.c
index aa6a217..7ee0f54 100644
--- a/board/freescale/t4qds/t4qds.c
+++ b/board/freescale/t4qds/t4240qds.c
@@ -43,12 +43,11 @@
char buf[64];
u8 sw;
struct cpu_type *cpu = gd->arch.cpu;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
unsigned int i;
printf("Board: %sQDS, ", cpu->name);
printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
- QIXIS_READ(id), QIXIS_READ(arch));
+ QIXIS_READ(id), QIXIS_READ(arch));
sw = QIXIS_READ(brdcfg[0]);
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
@@ -63,24 +62,11 @@
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
printf("FPGA: v%d (%s), build %d",
- (int)QIXIS_READ(scver), qixis_read_tag(buf),
- (int)qixis_read_minor());
+ (int)QIXIS_READ(scver), qixis_read_tag(buf),
+ (int)qixis_read_minor());
/* the timestamp string contains "\n" at the end */
printf(" on %s", qixis_read_time(buf));
- /* Display the RCW, so that no one gets confused as to what RCW
- * we're actually using for this boot.
- */
- puts("Reset Configuration Word (RCW):");
- for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
- u32 rcw = in_be32(&gur->rcwsr[i]);
-
- if ((i % 4) == 0)
- printf("\n %08x:", i * 4);
- printf(" %08x", rcw);
- }
- puts("\n");
-
/*
* Display the actual SERDES reference clocks as configured by the
* dip switches on the board. Note that the SWx registers could
@@ -92,7 +78,7 @@
puts("SERDES Reference Clocks: ");
sw = QIXIS_READ(brdcfg[2]);
for (i = 0; i < MAX_SERDES; i++) {
- static const char *freq[] = {
+ static const char * const freq[] = {
"100", "125", "156.25", "161.1328125"};
unsigned int clock = (sw >> (6 - 2 * i)) & 3;
@@ -430,7 +416,7 @@
break;
default:
printf("WARNING: unsupported for SerDes3 Protocol %d\n",
- srds_prtcl_s3);
+ srds_prtcl_s3);
return -1;
}
@@ -470,7 +456,7 @@
break;
default:
printf("WARNING: unsupported for SerDes4 Protocol %d\n",
- srds_prtcl_s4);
+ srds_prtcl_s4);
return -1;
}
@@ -495,8 +481,8 @@
disable_tlb(flash_esel);
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
set_liodns();
#ifdef CONFIG_SYS_DPAA_QBMAN
@@ -634,9 +620,8 @@
u32 pllcr0 = srds_regs->bank[i].pllcr0;
u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
if (expected != actual[i]) {
- printf("Warning: SERDES%u expects reference clock"
- " %sMHz, but actual is %sMHz\n", i + 1,
- serdes_clock_to_string(expected),
+ printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n",
+ i + 1, serdes_clock_to_string(expected),
serdes_clock_to_string(actual[i]));
}
}
@@ -795,42 +780,44 @@
}
sw[0] = dutcfg[0];
- sw[1] = (dutcfg[1] << 0x07) | \
- ((dutcfg[12] & 0xC0) >> 1) | \
- ((dutcfg[11] & 0xE0) >> 3) | \
- ((dutcfg[6] & 0x80) >> 6) | \
+ sw[1] = (dutcfg[1] << 0x07) |
+ ((dutcfg[12] & 0xC0) >> 1) |
+ ((dutcfg[11] & 0xE0) >> 3) |
+ ((dutcfg[6] & 0x80) >> 6) |
((dutcfg[1] & 0x80) >> 7);
- sw[2] = ((brdcfg[1] & 0x0f) << 4) | \
- ((brdcfg[1] & 0x30) >> 2) | \
- ((brdcfg[1] & 0x40) >> 5) | \
+ sw[2] = ((brdcfg[1] & 0x0f) << 4) |
+ ((brdcfg[1] & 0x30) >> 2) |
+ ((brdcfg[1] & 0x40) >> 5) |
((brdcfg[1] & 0x80) >> 7);
sw[3] = brdcfg[2];
- sw[4] = ((dutcfg[2] & 0x01) << 7) | \
- ((dutcfg[2] & 0x06) << 4) | \
- ((~QIXIS_READ(present)) & 0x10) | \
- ((brdcfg[3] & 0x80) >> 4) | \
- ((brdcfg[3] & 0x01) << 2) | \
- ((brdcfg[6] == 0x62) ? 3 : \
- ((brdcfg[6] == 0x5a) ? 2 : \
+ sw[4] = ((dutcfg[2] & 0x01) << 7) |
+ ((dutcfg[2] & 0x06) << 4) |
+ ((~QIXIS_READ(present)) & 0x10) |
+ ((brdcfg[3] & 0x80) >> 4) |
+ ((brdcfg[3] & 0x01) << 2) |
+ ((brdcfg[6] == 0x62) ? 3 :
+ ((brdcfg[6] == 0x5a) ? 2 :
((brdcfg[6] == 0x5e) ? 1 : 0)));
- sw[5] = ((brdcfg[0] & 0x0f) << 4) | \
- ((QIXIS_READ(rst_ctl) & 0x30) >> 2) | \
+ sw[5] = ((brdcfg[0] & 0x0f) << 4) |
+ ((QIXIS_READ(rst_ctl) & 0x30) >> 2) |
((brdcfg[0] & 0x40) >> 5);
sw[6] = (brdcfg[11] & 0x20) |
((brdcfg[5] & 0x02) << 3);
- sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) | \
+ sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) |
((brdcfg[5] & 0x10) << 2);
- sw[8] = ((brdcfg[12] & 0x08) << 4) | \
+ sw[8] = ((brdcfg[12] & 0x08) << 4) |
((brdcfg[12] & 0x03) << 5);
puts("DIP switch (reverse-engineering)\n");
for (i = 0; i < 9; i++) {
printf("SW%d = 0b%s (0x%02x)\n",
- i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
+ i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
}
}
-static int do_vdd_adjust(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_vdd_adjust(cmd_tbl_t *cmdtp,
+ int flag, int argc,
+ char * const argv[])
{
ulong override;
diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c
index b27356a..b701e75 100644
--- a/board/freescale/t4qds/tlb.c
+++ b/board/freescale/t4qds/tlb.c
@@ -120,9 +120,11 @@
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_64K, 1),
#endif
+#ifdef QIXIS_BASE_PHYS
SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 17, BOOKE_PAGESZ_4K, 1),
+#endif
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/*
* SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
diff --git a/boards.cfg b/boards.cfg
index 944ed4c..d6e29fa 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -775,6 +775,8 @@
MPC8572DS powerpc mpc85xx mpc8572ds freescale - MPC8572DS
MPC8572DS_36BIT powerpc mpc85xx mpc8572ds freescale - MPC8572DS:36BIT
MPC8572DS_NAND powerpc mpc85xx mpc8572ds freescale - MPC8572DS:NAND
+C29XPCIE powerpc mpc85xx c29xpcie freescale - C29XPCIE:C29XPCIE,36BIT
+C29XPCIE_SPIFLASH powerpc mpc85xx c29xpcie freescale - C29XPCIE:C29XPCIE,36BIT,SPIFLASH
P1010RDB_36BIT_NAND powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,NAND
P1010RDB_36BIT_NAND_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,NAND_SECBOOT,SECURE_BOOT
P1010RDB_36BIT_NOR powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT
@@ -805,16 +807,20 @@
P1020RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,36BIT,SDCARD
P1020RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,36BIT,SPIFLASH
P1020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,NAND
-P1020RDB-PC powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB
-P1020RDB-PC_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,36BIT
-P1020RDB-PC_36BIT_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,36BIT,NAND
-P1020RDB-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,36BIT,SDCARD
-P1020RDB-PC_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,36BIT,SPIFLASH
-P1020RDB-PC_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,NAND
-P1020RDB-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,SDCARD
-P1020RDB-PC_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,SPIFLASH
+P1020RDB-PC powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PC
+P1020RDB-PC_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PC,36BIT
+P1020RDB-PC_36BIT_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PC,36BIT,NAND
+P1020RDB-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PC,36BIT,SDCARD
+P1020RDB-PC_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PC,36BIT,SPIFLASH
+P1020RDB-PC_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PC,NAND
+P1020RDB-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PC,SDCARD
+P1020RDB-PC_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PC,SPIFLASH
P1020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SDCARD
P1020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SPIFLASH
+P1020RDB-PD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PD
+P1020RDB-PD_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PD,NAND
+P1020RDB-PD_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PD,SDCARD
+P1020RDB-PD_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PD,SPIFLASH
P1020UTM-PC powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020UTM
P1020UTM-PC_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020UTM,36BIT
P1020UTM-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020UTM,36BIT,SDCARD
@@ -848,6 +854,7 @@
P1025RDB_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1025RDB,NAND
P1025RDB_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1025RDB,SDCARD
P1025RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1025RDB,SPIFLASH
+TWR-P1025 powerpc mpc85xx p1_twr freescale - p1_twr:TWR_P1025
P2010RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB
P2010RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT
P2010RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT,SDCARD
@@ -924,6 +931,7 @@
stxssa powerpc mpc85xx stxssa stx - stxssa
stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M
T4240QDS powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240
+T4240EMU powerpc mpc85xx t4qds freescale - T4240EMU:PPC_T4240
T4240QDS_SDCARD powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
T4240QDS_SPIFLASH powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
T4240QDS_SRIO_PCIE_BOOT powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
diff --git a/common/lcd.c b/common/lcd.c
index 8d5c63c..990650c 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -51,7 +51,6 @@
/* ** FONT DATA */
/************************************************************************/
#include <video_font.h> /* Get font data, width and height */
-#include <video_font_data.h>
/************************************************************************/
/* ** LOGO DATA */
diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
index 96d4c9b..22defcd 100644
--- a/drivers/dma/apbh_dma.c
+++ b/drivers/dma/apbh_dma.c
@@ -545,6 +545,28 @@
}
/*
+ * Execute a continuously running circular DMA descriptor.
+ * NOTE: This is not intended for general use, but rather
+ * for the LCD driver in Smart-LCD mode. It allows
+ * continuous triggering of the RUN bit there.
+ */
+void mxs_dma_circ_start(int chan, struct mxs_dma_desc *pdesc)
+{
+ struct mxs_apbh_regs *apbh_regs =
+ (struct mxs_apbh_regs *)MXS_APBH_BASE;
+
+ mxs_dma_flush_desc(pdesc);
+
+ mxs_dma_enable_irq(chan, 1);
+
+ writel(mxs_dma_cmd_address(pdesc),
+ &apbh_regs->ch[chan].hw_apbh_ch_nxtcmdar);
+ writel(1, &apbh_regs->ch[chan].hw_apbh_ch_sema);
+ writel(1 << (chan + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),
+ &apbh_regs->hw_apbh_ctrl0_clr);
+}
+
+/*
* Initialize the DMA hardware
*/
void mxs_dma_init(void)
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index 4bc8f35..bca20b3 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -396,6 +396,8 @@
}
#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE)
void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR;
+#else
+ void *addr = NULL;
#endif
/* Upload the Fman microcode if it's present */
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 17ca961..d55db1a 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -28,12 +28,6 @@
#include <asm/io.h>
#include <asm/fsl_pci.h>
-/* Freescale-specific PCI config registers */
-#define FSL_PCI_PBFR 0x44
-#define FSL_PCIE_CAP_ID 0x4c
-#define FSL_PCIE_CFG_RDY 0x4b0
-#define FSL_PROG_IF_AGENT 0x1
-
#ifndef CONFIG_SYS_PCI_MEMORY_BUS
#define CONFIG_SYS_PCI_MEMORY_BUS 0
#endif
@@ -424,6 +418,15 @@
udelay(1);
#endif
if (pcie_cap == PCI_CAP_ID_EXP) {
+ if (block_rev >= PEX_IP_BLK_REV_3_0) {
+#define PEX_CSR0_LTSSM_MASK 0xFC
+#define PEX_CSR0_LTSSM_SHIFT 2
+ ltssm = (in_be32(&pci->pex_csr0)
+ & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
+ enabled = (ltssm == 0x11) ? 1 : 0;
+ } else {
+ /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); */
+ /* enabled = ltssm >= PCI_LTSSM_L0; */
pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
enabled = ltssm >= PCI_LTSSM_L0;
@@ -456,6 +459,7 @@
PCI_BASE_ADDRESS_0, pcicsrbar);
}
#endif
+ }
#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
if (enabled == 0) {
@@ -564,6 +568,10 @@
u8 prog_if;
pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);
+ /* Programming Interface (PCI_CLASS_PROG)
+ * 0 == pci host or pcie root-complex,
+ * 1 == pci agent or pcie end-point
+ */
return (prog_if == FSL_PROG_IF_AGENT);
}
}
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index f1fb26c..6dee1e9 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -19,6 +19,7 @@
exynos_mipi_dsi_lowlevel.o
COBJS-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o
COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
+COBJS-$(CONFIG_L5F31188) += l5f31188.o
COBJS-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o
COBJS-$(CONFIG_PXA_LCD) += pxa_lcd.o
COBJS-$(CONFIG_S6E8AX0) += s6e8ax0.o
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index 96ef8f9..fd28855 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -197,7 +197,6 @@
#include <linux/types.h>
#include <stdio_dev.h>
#include <video_font.h>
-#include <video_font_data.h>
#if defined(CONFIG_CMD_DATE)
#include <rtc.h>
@@ -431,6 +430,16 @@
{0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff}
};
+/*
+ * Implement a weak default function for boards that optionally
+ * need to skip the cfb initialization.
+ */
+__weak int board_cfb_skip(void)
+{
+ /* As default, don't skip cfb init */
+ return 0;
+}
+
static void video_drawchars(int xx, int yy, unsigned char *s, int count)
{
u8 *cdat, *dest, *dest0;
@@ -452,6 +461,10 @@
((u32 *) dest)[0] =
(video_font_draw_table8[bits >> 4] &
eorx) ^ bgx;
+
+ if (VIDEO_FONT_WIDTH == 4)
+ continue;
+
((u32 *) dest)[1] =
(video_font_draw_table8[bits & 15] &
eorx) ^ bgx;
@@ -477,6 +490,10 @@
SHORTSWAP32((video_font_draw_table15
[bits >> 4 & 3] & eorx) ^
bgx);
+
+ if (VIDEO_FONT_WIDTH == 4)
+ continue;
+
((u32 *) dest)[2] =
SHORTSWAP32((video_font_draw_table15
[bits >> 2 & 3] & eorx) ^
@@ -507,6 +524,10 @@
SHORTSWAP32((video_font_draw_table16
[bits >> 4 & 3] & eorx) ^
bgx);
+
+ if (VIDEO_FONT_WIDTH == 4)
+ continue;
+
((u32 *) dest)[2] =
SHORTSWAP32((video_font_draw_table16
[bits >> 2 & 3] & eorx) ^
@@ -541,6 +562,11 @@
((u32 *) dest)[3] =
SWAP32((video_font_draw_table32
[bits >> 4][3] & eorx) ^ bgx);
+
+
+ if (VIDEO_FONT_WIDTH == 4)
+ continue;
+
((u32 *) dest)[4] =
SWAP32((video_font_draw_table32
[bits & 15][0] & eorx) ^ bgx);
@@ -576,6 +602,10 @@
((u32 *) dest)[2] =
(video_font_draw_table24[bits >> 4][2]
& eorx) ^ bgx;
+
+ if (VIDEO_FONT_WIDTH == 4)
+ continue;
+
((u32 *) dest)[3] =
(video_font_draw_table24[bits & 15][0]
& eorx) ^ bgx;
@@ -1996,6 +2026,8 @@
return video_fb_address + video_logo_height * VIDEO_LINE_LEN;
}
#endif
+ if (board_cfb_skip())
+ return 0;
sprintf(info, " %s", version_string);
@@ -2205,6 +2237,9 @@
/* Init video chip - returns with framebuffer cleared */
skip_dev_init = (video_init() == -1);
+ if (board_cfb_skip())
+ return 0;
+
#if !defined(CONFIG_VGA_AS_SINGLE_DEVICE)
debug("KBD: Keyboard init ...\n");
skip_dev_init |= (VIDEO_KBD_INIT_FCT == -1);
diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c
index 373991dd..3a5f325 100644
--- a/drivers/video/da8xx-fb.c
+++ b/drivers/video/da8xx-fb.c
@@ -24,10 +24,17 @@
#include <asm/arch/hardware.h>
#include "videomodes.h"
-#include <asm/arch/da8xx-fb.h>
+#include "da8xx-fb.h"
+
+#if !defined(DA8XX_LCD_CNTL_BASE)
+#define DA8XX_LCD_CNTL_BASE DAVINCI_LCD_CNTL_BASE
+#endif
#define DRIVER_NAME "da8xx_lcdc"
+#define LCD_VERSION_1 1
+#define LCD_VERSION_2 2
+
/* LCD Status Register */
#define LCD_END_OF_FRAME1 (1 << 9)
#define LCD_END_OF_FRAME0 (1 << 8)
@@ -42,9 +49,14 @@
#define LCD_DMA_BURST_4 0x2
#define LCD_DMA_BURST_8 0x3
#define LCD_DMA_BURST_16 0x4
-#define LCD_END_OF_FRAME_INT_ENA (1 << 2)
+#define LCD_V1_END_OF_FRAME_INT_ENA (1 << 2)
+#define LCD_V2_END_OF_FRAME0_INT_ENA (1 << 8)
+#define LCD_V2_END_OF_FRAME1_INT_ENA (1 << 9)
#define LCD_DUAL_FRAME_BUFFER_ENABLE (1 << 0)
+#define LCD_V2_TFT_24BPP_MODE (1 << 25)
+#define LCD_V2_TFT_24BPP_UNPACK (1 << 26)
+
/* LCD Control Register */
#define LCD_CLK_DIVISOR(x) ((x) << 8)
#define LCD_RASTER_MODE 0x01
@@ -58,12 +70,20 @@
#define LCD_MONO_8BIT_MODE (1 << 9)
#define LCD_RASTER_ORDER (1 << 8)
#define LCD_TFT_MODE (1 << 7)
-#define LCD_UNDERFLOW_INT_ENA (1 << 6)
-#define LCD_PL_ENABLE (1 << 4)
+#define LCD_V1_UNDERFLOW_INT_ENA (1 << 6)
+#define LCD_V2_UNDERFLOW_INT_ENA (1 << 5)
+#define LCD_V1_PL_INT_ENA (1 << 4)
+#define LCD_V2_PL_INT_ENA (1 << 6)
#define LCD_MONOCHROME_MODE (1 << 1)
#define LCD_RASTER_ENABLE (1 << 0)
#define LCD_TFT_ALT_ENABLE (1 << 23)
#define LCD_STN_565_ENABLE (1 << 24)
+#define LCD_V2_DMA_CLK_EN (1 << 2)
+#define LCD_V2_LIDD_CLK_EN (1 << 1)
+#define LCD_V2_CORE_CLK_EN (1 << 0)
+#define LCD_V2_LPP_B10 26
+#define LCD_V2_TFT_24BPP_MODE (1 << 25)
+#define LCD_V2_TFT_24BPP_UNPACK (1 << 26)
/* LCD Raster Timing 2 Register */
#define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
@@ -74,6 +94,8 @@
#define LCD_INVERT_LINE_CLOCK (1 << 21)
#define LCD_INVERT_FRAME_CLOCK (1 << 20)
+/* Clock registers available only on Version 2 */
+#define LCD_CLK_MAIN_RESET (1 << 3)
/* LCD Block */
struct da8xx_lcd_regs {
u32 revid;
@@ -97,6 +119,15 @@
u32 dma_frm_buf_ceiling_addr_0;
u32 dma_frm_buf_base_addr_1;
u32 dma_frm_buf_ceiling_addr_1;
+ u32 resv1;
+ u32 raw_stat;
+ u32 masked_stat;
+ u32 int_ena_set;
+ u32 int_ena_clr;
+ u32 end_of_int_ind;
+ /* Clock registers available only on Version 2 */
+ u32 clk_ena;
+ u32 clk_reset;
};
#define LCD_NUM_BUFFERS 1
@@ -107,6 +138,8 @@
#define RIGHT_MARGIN 64
#define UPPER_MARGIN 32
#define LOWER_MARGIN 32
+#define WAIT_FOR_FRAME_DONE true
+#define NO_WAIT_FOR_FRAME_DONE false
#define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP)
@@ -119,6 +152,8 @@
static const struct da8xx_panel *lcd_panel;
static struct fb_info *da8xx_fb_info;
static int bits_x_pixel;
+static unsigned int lcd_revision;
+const struct lcd_ctrl_config *da8xx_lcd_cfg;
static inline unsigned int lcdc_read(u32 *addr)
{
@@ -179,35 +214,24 @@
.accel = FB_ACCEL_NONE
};
-static const struct display_panel disp_panel = {
- QVGA,
- 16,
- 16,
- COLOR_ACTIVE,
-};
-
-static const struct lcd_ctrl_config lcd_cfg = {
- &disp_panel,
- .ac_bias = 255,
- .ac_bias_intrpt = 0,
- .dma_burst_sz = 16,
- .bpp = 16,
- .fdd = 255,
- .tft_alt_mode = 0,
- .stn_565_mode = 0,
- .mono_8bit_mode = 0,
- .invert_line_clock = 1,
- .invert_frm_clock = 1,
- .sync_edge = 0,
- .sync_ctrl = 1,
- .raster_order = 0,
-};
-
/* Enable the Raster Engine of the LCD Controller */
static inline void lcd_enable_raster(void)
{
u32 reg;
+ /* Put LCDC in reset for several cycles */
+ if (lcd_revision == LCD_VERSION_2)
+ lcdc_write(LCD_CLK_MAIN_RESET,
+ &da8xx_fb_reg_base->clk_reset);
+
+ udelay(1000);
+ /* Bring LCDC out of reset */
+ if (lcd_revision == LCD_VERSION_2)
+ lcdc_write(0,
+ &da8xx_fb_reg_base->clk_reset);
+
+ udelay(1000);
+
reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
if (!(reg & LCD_RASTER_ENABLE))
lcdc_write(reg | LCD_RASTER_ENABLE,
@@ -215,14 +239,40 @@
}
/* Disable the Raster Engine of the LCD Controller */
-static inline void lcd_disable_raster(void)
+static inline void lcd_disable_raster(bool wait_for_frame_done)
{
u32 reg;
+ u32 loop_cnt = 0;
+ u32 stat;
+ u32 i = 0;
+
+ if (wait_for_frame_done)
+ loop_cnt = 5000;
reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
if (reg & LCD_RASTER_ENABLE)
lcdc_write(reg & ~LCD_RASTER_ENABLE,
&da8xx_fb_reg_base->raster_ctrl);
+
+ /* Wait for the current frame to complete */
+ do {
+ if (lcd_revision == LCD_VERSION_1)
+ stat = lcdc_read(&da8xx_fb_reg_base->stat);
+ else
+ stat = lcdc_read(&da8xx_fb_reg_base->raw_stat);
+
+ mdelay(1);
+ } while (!(stat & 0x01) && (i++ < loop_cnt));
+
+ if (lcd_revision == LCD_VERSION_1)
+ lcdc_write(stat, &da8xx_fb_reg_base->stat);
+ else
+ lcdc_write(stat, &da8xx_fb_reg_base->raw_stat);
+
+ if ((loop_cnt != 0) && (i >= loop_cnt)) {
+ printf("LCD Controller timed out\n");
+ return;
+ }
}
static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
@@ -231,6 +281,7 @@
u32 end;
u32 reg_ras;
u32 reg_dma;
+ u32 reg_int;
/* init reg to clear PLM (loading mode) fields */
reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
@@ -243,7 +294,15 @@
end = par->dma_end;
reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
- reg_dma |= LCD_END_OF_FRAME_INT_ENA;
+ if (lcd_revision == LCD_VERSION_1) {
+ reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
+ } else {
+ reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
+ LCD_V2_END_OF_FRAME0_INT_ENA |
+ LCD_V2_END_OF_FRAME1_INT_ENA |
+ LCD_V2_UNDERFLOW_INT_ENA | LCD_SYNC_LOST;
+ lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
+ }
#if (LCD_NUM_BUFFERS == 2)
reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
@@ -264,7 +323,13 @@
end = start + par->palette_sz - 1;
reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
- reg_ras |= LCD_PL_ENABLE;
+ if (lcd_revision == LCD_VERSION_1) {
+ reg_ras |= LCD_V1_PL_INT_ENA;
+ } else {
+ reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
+ LCD_V2_PL_INT_ENA;
+ lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
+ }
lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
@@ -348,6 +413,7 @@
static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
{
u32 reg;
+ u32 reg_int;
reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE |
LCD_MONO_8BIT_MODE |
@@ -375,7 +441,13 @@
}
/* enable additional interrupts here */
- reg |= LCD_UNDERFLOW_INT_ENA;
+ if (lcd_revision == LCD_VERSION_1) {
+ reg |= LCD_V1_UNDERFLOW_INT_ENA;
+ } else {
+ reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
+ LCD_V2_UNDERFLOW_INT_ENA;
+ lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
+ }
lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
@@ -413,22 +485,53 @@
/* Set the Panel Width */
/* Pixels per line = (PPL + 1)*16 */
- /*0x3F in bits 4..9 gives max horisontal resolution = 1024 pixels*/
- width &= 0x3f0;
+ if (lcd_revision == LCD_VERSION_1) {
+ /*
+ * 0x3F in bits 4..9 gives max horisontal resolution = 1024
+ * pixels
+ */
+ width &= 0x3f0;
+ } else {
+ /*
+ * 0x7F in bits 4..10 gives max horizontal resolution = 2048
+ * pixels.
+ */
+ width &= 0x7f0;
+ }
reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0);
reg &= 0xfffffc00;
- reg |= ((width >> 4) - 1) << 4;
+ if (lcd_revision == LCD_VERSION_1) {
+ reg |= ((width >> 4) - 1) << 4;
+ } else {
+ width = (width >> 4) - 1;
+ reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
+ }
lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
/* Set the Panel Height */
+ /* Set bits 9:0 of Lines Per Pixel */
reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1);
reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
+ /* Set bit 10 of Lines Per Pixel */
+ if (lcd_revision == LCD_VERSION_2) {
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
+ reg |= ((height - 1) & 0x400) << 16;
+ lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
+ }
+
/* Set the Raster Order of the Frame Buffer */
reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8);
if (raster_order)
reg |= LCD_RASTER_ORDER;
+
+ if (bpp == 24)
+ reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE);
+ else if (bpp == 32)
+ reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE
+ | LCD_V2_TFT_24BPP_UNPACK);
+
lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
switch (bpp) {
@@ -436,6 +539,8 @@
case 2:
case 4:
case 16:
+ case 24:
+ case 32:
par->palette_sz = 16 * 2;
break;
@@ -494,6 +599,23 @@
update_hw = 1;
palette[0] = 0x4000;
}
+ } else if (((info->var.bits_per_pixel == 32) && regno < 32) ||
+ ((info->var.bits_per_pixel == 24) && regno < 24)) {
+ red >>= (24 - info->var.red.length);
+ red <<= info->var.red.offset;
+
+ green >>= (24 - info->var.green.length);
+ green <<= info->var.green.offset;
+
+ blue >>= (24 - info->var.blue.length);
+ blue <<= info->var.blue.offset;
+
+ par->pseudo_palette[regno] = red | green | blue;
+
+ if (palette[0] != 0x4000) {
+ update_hw = 1;
+ palette[0] = 0x4000;
+ }
}
/* Update the palette in the h/w as needed. */
@@ -506,11 +628,18 @@
static void lcd_reset(struct da8xx_fb_par *par)
{
/* Disable the Raster if previously Enabled */
- lcd_disable_raster();
+ lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
/* DMA has to be disabled */
lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl);
lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl);
+
+ if (lcd_revision == LCD_VERSION_2) {
+ lcdc_write(0, &da8xx_fb_reg_base->int_ena_set);
+ /* Write 1 to reset */
+ lcdc_write(LCD_CLK_MAIN_RESET, &da8xx_fb_reg_base->clk_reset);
+ lcdc_write(0, &da8xx_fb_reg_base->clk_reset);
+ }
}
static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
@@ -521,12 +650,17 @@
lcd_clk = clk_get(2);
div = lcd_clk / par->pxl_clk;
- debug("LCD Clock: 0x%x Divider: 0x%x PixClk: 0x%x\n",
- lcd_clk, div, par->pxl_clk);
+ debug("LCD Clock: %d Divider: %d PixClk: %d\n",
+ lcd_clk, div, par->pxl_clk);
/* Configure the LCD clock divisor. */
lcdc_write(LCD_CLK_DIVISOR(div) |
(LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl);
+
+ if (lcd_revision == LCD_VERSION_2)
+ lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
+ LCD_V2_CORE_CLK_EN,
+ &da8xx_fb_reg_base->clk_ena);
}
static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
@@ -566,7 +700,8 @@
if (ret < 0)
return ret;
- if (QVGA != cfg->p_disp_panel->panel_type)
+ if ((QVGA != cfg->p_disp_panel->panel_type) &&
+ (WVGA != cfg->p_disp_panel->panel_type))
return -EINVAL;
if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
@@ -602,7 +737,7 @@
&da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
}
-static u32 lcdc_irq_handler(void)
+static u32 lcdc_irq_handler_rev01(void)
{
struct da8xx_fb_par *par = da8xx_fb_info->par;
u32 stat = lcdc_read(&da8xx_fb_reg_base->stat);
@@ -610,7 +745,7 @@
if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
debug("LCD_SYNC_LOST\n");
- lcd_disable_raster();
+ lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
lcdc_write(stat, &da8xx_fb_reg_base->stat);
lcd_enable_raster();
return LCD_SYNC_LOST;
@@ -622,13 +757,13 @@
* interrupt via the following write to the status register. If
* this is done after then one gets multiple PL done interrupts.
*/
- lcd_disable_raster();
+ lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
lcdc_write(stat, &da8xx_fb_reg_base->stat);
/* Disable PL completion inerrupt */
reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
- reg_ras &= ~LCD_PL_ENABLE;
+ reg_ras &= ~LCD_V1_PL_INT_ENA;
lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
/* Setup and start data loading mode */
@@ -650,6 +785,66 @@
return stat;
}
+static u32 lcdc_irq_handler_rev02(void)
+{
+ struct da8xx_fb_par *par = da8xx_fb_info->par;
+ u32 stat = lcdc_read(&da8xx_fb_reg_base->masked_stat);
+ u32 reg_int;
+
+ if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
+ debug("LCD_SYNC_LOST\n");
+ lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
+ lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
+ lcd_enable_raster();
+ lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
+ return LCD_SYNC_LOST;
+ } else if (stat & LCD_PL_LOAD_DONE) {
+ debug("LCD_PL_LOAD_DONE\n");
+ /*
+ * Must disable raster before changing state of any control bit.
+ * And also must be disabled before clearing the PL loading
+ * interrupt via the following write to the status register. If
+ * this is done after then one gets multiple PL done interrupts.
+ */
+ lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
+
+ lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
+
+ /* Disable PL completion inerrupt */
+ reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_clr) |
+ (LCD_V2_PL_INT_ENA);
+ lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_clr);
+
+ /* Setup and start data loading mode */
+ lcd_blit(LOAD_DATA, par);
+ lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
+ return LCD_PL_LOAD_DONE;
+ } else {
+ lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
+
+ if (stat & LCD_END_OF_FRAME0)
+ debug("LCD_END_OF_FRAME0\n");
+
+ lcdc_write(par->dma_start,
+ &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+ lcdc_write(par->dma_end,
+ &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+ par->vsync_flag = 1;
+ lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
+ return LCD_END_OF_FRAME0;
+ }
+ lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
+ return stat;
+}
+
+static u32 lcdc_irq_handler(void)
+{
+ if (lcd_revision == LCD_VERSION_1)
+ return lcdc_irq_handler_rev01();
+ else
+ return lcdc_irq_handler_rev02();
+}
+
static u32 wait_for_event(u32 event)
{
u32 timeout = 50000;
@@ -673,6 +868,7 @@
{
struct da8xx_fb_par *par;
u32 size;
+ u32 rev;
char *p;
if (!lcd_panel) {
@@ -685,6 +881,10 @@
gpanel.plnSizeY = lcd_panel->height;
switch (bits_x_pixel) {
+ case 32:
+ gpanel.gdfBytesPP = 4;
+ gpanel.gdfIndex = GDF_32BIT_X888RGB;
+ break;
case 24:
gpanel.gdfBytesPP = 4;
gpanel.gdfIndex = GDF_32BIT_X888RGB;
@@ -699,12 +899,29 @@
break;
}
- da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DAVINCI_LCD_CNTL_BASE;
+ da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DA8XX_LCD_CNTL_BASE;
- debug("Resolution: %dx%d %x\n",
- gpanel.winSizeX,
- gpanel.winSizeY,
- lcd_cfg.bpp);
+ /* Determine LCD IP Version */
+ rev = lcdc_read(&da8xx_fb_reg_base->revid);
+ switch (rev) {
+ case 0x4C100102:
+ lcd_revision = LCD_VERSION_1;
+ break;
+ case 0x4F200800:
+ case 0x4F201000:
+ lcd_revision = LCD_VERSION_2;
+ break;
+ default:
+ printf("Unknown PID Reg value 0x%x, defaulting to LCD revision 1\n",
+ rev);
+ lcd_revision = LCD_VERSION_1;
+ break;
+ }
+
+ debug("rev: 0x%x Resolution: %dx%d %d\n", rev,
+ gpanel.winSizeX,
+ gpanel.winSizeY,
+ da8xx_lcd_cfg->bpp);
size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par);
da8xx_fb_info = malloc(size);
@@ -722,13 +939,14 @@
par = da8xx_fb_info->par;
par->pxl_clk = lcd_panel->pxl_clk;
- if (lcd_init(par, &lcd_cfg, lcd_panel) < 0) {
+ if (lcd_init(par, da8xx_lcd_cfg, lcd_panel) < 0) {
printf("lcd_init failed\n");
goto err_release_fb;
}
/* allocate frame buffer */
- par->vram_size = lcd_panel->width * lcd_panel->height * lcd_cfg.bpp;
+ par->vram_size = lcd_panel->width * lcd_panel->height *
+ da8xx_lcd_cfg->bpp;
par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8;
par->vram_virt = malloc(par->vram_size);
@@ -741,12 +959,13 @@
printf("GLCD: malloc for frame buffer failed\n");
goto err_release_fb;
}
+ gd->fb_base = (int)par->vram_virt;
gpanel.frameAdrs = (unsigned int)par->vram_virt;
da8xx_fb_info->screen_base = (char *) par->vram_virt;
da8xx_fb_fix.smem_start = gpanel.frameAdrs;
da8xx_fb_fix.smem_len = par->vram_size;
- da8xx_fb_fix.line_length = (lcd_panel->width * lcd_cfg.bpp) / 8;
+ da8xx_fb_fix.line_length = (lcd_panel->width * da8xx_lcd_cfg->bpp) / 8;
par->dma_start = par->vram_phys;
par->dma_end = par->dma_start + lcd_panel->height *
@@ -762,7 +981,7 @@
par->p_palette_base = (unsigned int)par->v_palette_base;
/* Initialize par */
- da8xx_fb_info->var.bits_per_pixel = lcd_cfg.bpp;
+ da8xx_fb_info->var.bits_per_pixel = da8xx_lcd_cfg->bpp;
da8xx_fb_var.xres = lcd_panel->width;
da8xx_fb_var.xres_virtual = lcd_panel->width;
@@ -771,8 +990,8 @@
da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS;
da8xx_fb_var.grayscale =
- lcd_cfg.p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
- da8xx_fb_var.bits_per_pixel = lcd_cfg.bpp;
+ da8xx_lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
+ da8xx_fb_var.bits_per_pixel = da8xx_lcd_cfg->bpp;
da8xx_fb_var.hsync_len = lcd_panel->hsw;
da8xx_fb_var.vsync_len = lcd_panel->vsw;
@@ -787,8 +1006,11 @@
/* Clear interrupt */
memset((void *)par->vram_virt, 0, par->vram_size);
- lcd_disable_raster();
- lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);
+ lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
+ if (lcd_revision == LCD_VERSION_1)
+ lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);
+ else
+ lcdc_write(0xFFFF, &da8xx_fb_reg_base->masked_stat);
debug("Palette at 0x%x size %d\n", par->p_palette_base,
par->palette_sz);
lcdc_dma_start();
@@ -823,8 +1045,10 @@
return;
}
-void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel)
+void da8xx_video_init(const struct da8xx_panel *panel,
+ const struct lcd_ctrl_config *lcd_cfg, int bits_pixel)
{
lcd_panel = panel;
+ da8xx_lcd_cfg = lcd_cfg;
bits_x_pixel = bits_pixel;
}
diff --git a/arch/arm/include/asm/arch-davinci/da8xx-fb.h b/drivers/video/da8xx-fb.h
similarity index 93%
rename from arch/arm/include/asm/arch-davinci/da8xx-fb.h
rename to drivers/video/da8xx-fb.h
index c115034..6447a40 100644
--- a/arch/arm/include/asm/arch-davinci/da8xx-fb.h
+++ b/drivers/video/da8xx-fb.h
@@ -17,7 +17,8 @@
#define DA8XX_FB_H
enum panel_type {
- QVGA = 0
+ QVGA = 0,
+ WVGA
};
enum panel_shade {
@@ -108,6 +109,8 @@
int pulse_width;
};
-void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel);
+void da8xx_video_init(const struct da8xx_panel *panel,
+ const struct lcd_ctrl_config *lcd_cfg,
+ int bits_pixel);
#endif /* ifndef DA8XX_FB_H */
diff --git a/drivers/video/exynos_mipi_dsi_common.c b/drivers/video/exynos_mipi_dsi_common.c
index 2cc847f..97e1248 100644
--- a/drivers/video/exynos_mipi_dsi_common.c
+++ b/drivers/video/exynos_mipi_dsi_common.c
@@ -50,7 +50,7 @@
};
static void exynos_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim,
- unsigned int data0, unsigned int data1)
+ const unsigned char *data0, unsigned int data1)
{
unsigned int data_cnt = 0, payload = 0;
@@ -62,42 +62,40 @@
*/
if ((data1 - data_cnt) < 4) {
if ((data1 - data_cnt) == 3) {
- payload = *(u8 *)(data0 + data_cnt) |
- (*(u8 *)(data0 + (data_cnt + 1))) << 8 |
- (*(u8 *)(data0 + (data_cnt + 2))) << 16;
+ payload = data0[data_cnt] |
+ data0[data_cnt + 1] << 8 |
+ data0[data_cnt + 2] << 16;
debug("count = 3 payload = %x, %x %x %x\n",
- payload, *(u8 *)(data0 + data_cnt),
- *(u8 *)(data0 + (data_cnt + 1)),
- *(u8 *)(data0 + (data_cnt + 2)));
+ payload, data0[data_cnt],
+ data0[data_cnt + 1],
+ data0[data_cnt + 2]);
} else if ((data1 - data_cnt) == 2) {
- payload = *(u8 *)(data0 + data_cnt) |
- (*(u8 *)(data0 + (data_cnt + 1))) << 8;
+ payload = data0[data_cnt] |
+ data0[data_cnt + 1] << 8;
debug("count = 2 payload = %x, %x %x\n", payload,
- *(u8 *)(data0 + data_cnt),
- *(u8 *)(data0 + (data_cnt + 1)));
+ data0[data_cnt], data0[data_cnt + 1]);
} else if ((data1 - data_cnt) == 1) {
- payload = *(u8 *)(data0 + data_cnt);
+ payload = data0[data_cnt];
}
} else {
/* send 4bytes per one time. */
- payload = *(u8 *)(data0 + data_cnt) |
- (*(u8 *)(data0 + (data_cnt + 1))) << 8 |
- (*(u8 *)(data0 + (data_cnt + 2))) << 16 |
- (*(u8 *)(data0 + (data_cnt + 3))) << 24;
+ payload = data0[data_cnt] |
+ data0[data_cnt + 1] << 8 |
+ data0[data_cnt + 2] << 16 |
+ data0[data_cnt + 3] << 24;
debug("count = 4 payload = %x, %x %x %x %x\n",
payload, *(u8 *)(data0 + data_cnt),
- *(u8 *)(data0 + (data_cnt + 1)),
- *(u8 *)(data0 + (data_cnt + 2)),
- *(u8 *)(data0 + (data_cnt + 3)));
-
+ data0[data_cnt + 1],
+ data0[data_cnt + 2],
+ data0[data_cnt + 3]);
}
exynos_mipi_dsi_wr_tx_data(dsim, payload);
}
}
int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
- unsigned int data0, unsigned int data1)
+ const unsigned char *data0, unsigned int data1)
{
unsigned int timeout = TRY_GET_FIFO_TIMEOUT;
unsigned long delay_val, delay;
@@ -136,8 +134,8 @@
case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
debug("data0 = %x data1 = %x\n",
- data0, data1);
- exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0, data1);
+ data0[0], data0[1]);
+ exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
if (check_rx_ack) {
/* process response func should be implemented */
return 0;
@@ -150,7 +148,7 @@
case MIPI_DSI_COLOR_MODE_ON:
case MIPI_DSI_SHUTDOWN_PERIPHERAL:
case MIPI_DSI_TURN_ON_PERIPHERAL:
- exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0, data1);
+ exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
if (check_rx_ack) {
/* process response func should be implemented. */
return 0;
@@ -172,7 +170,7 @@
case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
case MIPI_DSI_DCS_READ:
exynos_mipi_dsi_clear_all_interrupt(dsim);
- exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0, data1);
+ exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
/* process response func should be implemented. */
return 0;
@@ -183,21 +181,19 @@
case MIPI_DSI_GENERIC_LONG_WRITE:
case MIPI_DSI_DCS_LONG_WRITE:
{
- unsigned int data_cnt = 0, payload = 0;
+ unsigned int payload = 0;
/* if data count is less then 4, then send 3bytes data. */
if (data1 < 4) {
- payload = *(u8 *)(data0) |
- *(u8 *)(data0 + 1) << 8 |
- *(u8 *)(data0 + 2) << 16;
+ payload = data0[0] |
+ data0[1] << 8 |
+ data0[2] << 16;
exynos_mipi_dsi_wr_tx_data(dsim, payload);
debug("count = %d payload = %x,%x %x %x\n",
- data1, payload,
- *(u8 *)(data0 + data_cnt),
- *(u8 *)(data0 + (data_cnt + 1)),
- *(u8 *)(data0 + (data_cnt + 2)));
+ data1, payload, data0[0],
+ data0[1], data0[2]);
} else {
/* in case that data count is more then 4 */
exynos_mipi_dsi_long_data_wr(dsim, data0, data1);
diff --git a/drivers/video/exynos_mipi_dsi_common.h b/drivers/video/exynos_mipi_dsi_common.h
index 318c7ec..ef6510a 100644
--- a/drivers/video/exynos_mipi_dsi_common.h
+++ b/drivers/video/exynos_mipi_dsi_common.h
@@ -13,7 +13,7 @@
#define _EXYNOS_MIPI_DSI_COMMON_H
int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
- unsigned int data0, unsigned int data1);
+ const unsigned char *data0, unsigned int data1);
int exynos_mipi_dsi_pll_on(struct mipi_dsim_device *dsim, unsigned int enable);
unsigned long exynos_mipi_dsi_change_pll(struct mipi_dsim_device *dsim,
unsigned int pre_divider, unsigned int main_divider,
diff --git a/drivers/video/exynos_mipi_dsi_lowlevel.c b/drivers/video/exynos_mipi_dsi_lowlevel.c
index b47eee4..1313bce 100644
--- a/drivers/video/exynos_mipi_dsi_lowlevel.c
+++ b/drivers/video/exynos_mipi_dsi_lowlevel.c
@@ -600,7 +600,7 @@
}
void exynos_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim,
- unsigned int di, unsigned int data0, unsigned int data1)
+ unsigned int di, const unsigned char data0, const unsigned char data1)
{
struct exynos_mipi_dsim *mipi_dsim =
(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
diff --git a/drivers/video/exynos_mipi_dsi_lowlevel.h b/drivers/video/exynos_mipi_dsi_lowlevel.h
index 8a45954..59f6ce0 100644
--- a/drivers/video/exynos_mipi_dsi_lowlevel.h
+++ b/drivers/video/exynos_mipi_dsi_lowlevel.h
@@ -91,7 +91,7 @@
*dsim);
void _exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim);
void exynos_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim,
- unsigned int di, unsigned int data0, unsigned int data1);
+ unsigned int di, const unsigned char data0, const unsigned char data1);
void exynos_mipi_dsi_wr_tx_data(struct mipi_dsim_device *dsim,
unsigned int tx_data);
diff --git a/drivers/video/l5f31188.c b/drivers/video/l5f31188.c
new file mode 100644
index 0000000..3312dcf
--- /dev/null
+++ b/drivers/video/l5f31188.c
@@ -0,0 +1,192 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd. All rights reserved.
+ * Hyungwon Hwang <human.hwang@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/mipi_dsim.h>
+
+#define SCAN_FROM_LEFT_TO_RIGHT 0
+#define SCAN_FROM_RIGHT_TO_LEFT 1
+#define SCAN_FROM_TOP_TO_BOTTOM 0
+#define SCAN_FROM_BOTTOM_TO_TOP 1
+
+static void l5f31188_sleep_in(struct mipi_dsim_device *dev,
+ struct mipi_dsim_master_ops *ops)
+{
+ ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x10, 0x00);
+}
+
+static void l5f31188_sleep_out(struct mipi_dsim_device *dev,
+ struct mipi_dsim_master_ops *ops)
+{
+ ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x11, 0x00);
+}
+
+static void l5f31188_set_gamma(struct mipi_dsim_device *dev,
+ struct mipi_dsim_master_ops *ops)
+{
+ ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x26, 0x00);
+}
+
+static void l5f31188_display_off(struct mipi_dsim_device *dev,
+ struct mipi_dsim_master_ops *ops)
+{
+ ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x28, 0x00);
+}
+
+static void l5f31188_display_on(struct mipi_dsim_device *dev,
+ struct mipi_dsim_master_ops *ops)
+{
+ ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x29, 0x00);
+}
+
+static void l5f31188_ctl_memory_access(struct mipi_dsim_device *dev,
+ struct mipi_dsim_master_ops *ops,
+ int h_direction, int v_direction)
+{
+ ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x36,
+ (((h_direction & 0x1) << 1) | (v_direction & 0x1)));
+}
+
+static void l5f31188_set_pixel_format(struct mipi_dsim_device *dev,
+ struct mipi_dsim_master_ops *ops)
+{
+ ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x3A, 0x70);
+}
+
+static void l5f31188_write_disbv(struct mipi_dsim_device *dev,
+ struct mipi_dsim_master_ops *ops, unsigned int brightness)
+{
+ ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x51, brightness);
+}
+
+static void l5f31188_write_ctrld(struct mipi_dsim_device *dev,
+ struct mipi_dsim_master_ops *ops)
+{
+ ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x53, 0x2C);
+}
+
+static void l5f31188_write_cabc(struct mipi_dsim_device *dev,
+ struct mipi_dsim_master_ops *ops,
+ unsigned int wm_mode)
+{
+ ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x55, wm_mode);
+}
+
+static void l5f31188_write_cabcmb(struct mipi_dsim_device *dev,
+ struct mipi_dsim_master_ops *ops, unsigned int min_brightness)
+{
+ ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x5E,
+ min_brightness);
+}
+
+static void l5f31188_set_extension(struct mipi_dsim_device *dev,
+ struct mipi_dsim_master_ops *ops)
+{
+ const unsigned char data_to_send[] = {
+ 0xB9, 0xFF, 0x83, 0x94
+ };
+
+ ops->cmd_write(dev, MIPI_DSI_DCS_LONG_WRITE,
+ (unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
+}
+
+static void l5f31188_set_dgc_lut(struct mipi_dsim_device *dev,
+ struct mipi_dsim_master_ops *ops)
+{
+ const unsigned char data_to_send[] = {
+ 0xC1, 0x01, 0x00, 0x04, 0x0E, 0x18, 0x1E, 0x26,
+ 0x2F, 0x36, 0x3E, 0x47, 0x4E, 0x56, 0x5D, 0x65,
+ 0x6D, 0x75, 0x7D, 0x84, 0x8C, 0x94, 0x9C, 0xA4,
+ 0xAD, 0xB5, 0xBD, 0xC5, 0xCC, 0xD4, 0xDE, 0xE5,
+ 0xEE, 0xF7, 0xFF, 0x3F, 0x9A, 0xCE, 0xD4, 0x21,
+ 0xA1, 0x26, 0x54, 0x00, 0x00, 0x04, 0x0E, 0x19,
+ 0x1F, 0x27, 0x30, 0x37, 0x40, 0x48, 0x50, 0x58,
+ 0x60, 0x67, 0x6F, 0x77, 0x7F, 0x87, 0x8F, 0x97,
+ 0x9F, 0xA7, 0xB0, 0xB8, 0xC0, 0xC8, 0xCE, 0xD8,
+ 0xE0, 0xE7, 0xF0, 0xF7, 0xFF, 0x3C, 0xEB, 0xFD,
+ 0x2F, 0x66, 0xA8, 0x2C, 0x46, 0x00, 0x00, 0x04,
+ 0x0E, 0x18, 0x1E, 0x26, 0x30, 0x38, 0x41, 0x4A,
+ 0x52, 0x5A, 0x62, 0x6B, 0x73, 0x7B, 0x83, 0x8C,
+ 0x94, 0x9C, 0xA5, 0xAD, 0xB6, 0xBD, 0xC5, 0xCC,
+ 0xD4, 0xDD, 0xE3, 0xEB, 0xF2, 0xF9, 0xFF, 0x3F,
+ 0xA4, 0x8A, 0x8F, 0xC7, 0x33, 0xF5, 0xE9, 0x00
+ };
+ ops->cmd_write(dev, MIPI_DSI_DCS_LONG_WRITE,
+ (unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
+}
+
+static void l5f31188_set_tcon(struct mipi_dsim_device *dev,
+ struct mipi_dsim_master_ops *ops)
+{
+ const unsigned char data_to_send[] = {
+ 0xC7, 0x00, 0x20
+ };
+ ops->cmd_write(dev, MIPI_DSI_DCS_LONG_WRITE,
+ (unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
+}
+
+static void l5f31188_set_ptba(struct mipi_dsim_device *dev,
+ struct mipi_dsim_master_ops *ops)
+{
+ const unsigned char data_to_send[] = {
+ 0xBF, 0x06, 0x10
+ };
+ ops->cmd_write(dev, MIPI_DSI_DCS_LONG_WRITE,
+ (unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
+}
+
+static void l5f31188_set_eco(struct mipi_dsim_device *dev,
+ struct mipi_dsim_master_ops *ops)
+{
+ ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0xC6, 0x0C);
+}
+
+static int l5f31188_panel_init(struct mipi_dsim_device *dev)
+{
+ struct mipi_dsim_master_ops *ops = dev->master_ops;
+
+ l5f31188_set_extension(dev, ops);
+ l5f31188_set_dgc_lut(dev, ops);
+
+ l5f31188_set_eco(dev, ops);
+ l5f31188_set_tcon(dev, ops);
+ l5f31188_set_ptba(dev, ops);
+ l5f31188_set_gamma(dev, ops);
+ l5f31188_ctl_memory_access(dev, ops,
+ SCAN_FROM_LEFT_TO_RIGHT, SCAN_FROM_TOP_TO_BOTTOM);
+ l5f31188_set_pixel_format(dev, ops);
+ l5f31188_write_disbv(dev, ops, 0xFF);
+ l5f31188_write_ctrld(dev, ops);
+ l5f31188_write_cabc(dev, ops, 0x0);
+ l5f31188_write_cabcmb(dev, ops, 0x0);
+
+ l5f31188_sleep_out(dev, ops);
+
+ /* 120 msec */
+ udelay(120 * 1000);
+
+ return 0;
+}
+
+static void l5f31188_display_enable(struct mipi_dsim_device *dev)
+{
+ struct mipi_dsim_master_ops *ops = dev->master_ops;
+ l5f31188_display_on(dev, ops);
+}
+
+static struct mipi_dsim_lcd_driver l5f31188_dsim_ddi_driver = {
+ .name = "l5f31188",
+ .id = -1,
+
+ .mipi_panel_init = l5f31188_panel_init,
+ .mipi_display_on = l5f31188_display_enable,
+};
+
+void l5f31188_init(void)
+{
+ exynos_mipi_dsi_register_lcd_driver(&l5f31188_dsim_ddi_driver);
+}
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 6bf9fc5..03b0f88 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -15,11 +15,25 @@
#include <asm/errno.h>
#include <asm/io.h>
+#include <asm/imx-common/dma.h>
+
#include "videomodes.h"
#define PS2KHZ(ps) (1000000000UL / (ps))
static GraphicDevice panel;
+struct mxs_dma_desc desc;
+
+/**
+ * mxsfb_system_setup() - Fine-tune LCDIF configuration
+ *
+ * This function is used to adjust the LCDIF configuration. This is usually
+ * needed when driving the controller in System-Mode to operate an 8080 or
+ * 6800 connected SmartLCD.
+ */
+__weak void mxsfb_system_setup(void)
+{
+}
/*
* DENX M28EVK:
@@ -75,6 +89,9 @@
writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
®s->hw_lcdif_ctrl1);
+
+ mxsfb_system_setup();
+
writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres,
®s->hw_lcdif_transfer_count);
@@ -102,8 +119,10 @@
/* Flush FIFO first */
writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_set);
+#ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM
/* Sync signals ON */
setbits_le32(®s->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
+#endif
/* FIFO cleared */
writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_clr);
@@ -161,7 +180,8 @@
panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
/* Allocate framebuffer */
- fb = malloc(panel.memSize);
+ fb = memalign(ARCH_DMA_MINALIGN,
+ roundup(panel.memSize, ARCH_DMA_MINALIGN));
if (!fb) {
printf("MXSFB: Error allocating framebuffer!\n");
return NULL;
@@ -177,5 +197,28 @@
/* Start framebuffer */
mxs_lcd_init(&panel, &mode, bpp);
+#ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
+ /*
+ * If the LCD runs in system mode, the LCD refresh has to be triggered
+ * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
+ * having to set this bit manually after every single change in the
+ * framebuffer memory, we set up specially crafted circular DMA, which
+ * sets the RUN bit, then waits until it gets cleared and repeats this
+ * infinitelly. This way, we get smooth continuous updates of the LCD.
+ */
+ struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
+
+ memset(&desc, 0, sizeof(struct mxs_dma_desc));
+ desc.address = (dma_addr_t)&desc;
+ desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
+ MXS_DMA_DESC_WAIT4END |
+ (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
+ desc.cmd.pio_words[0] = readl(®s->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
+ desc.cmd.next = (uint32_t)&desc.cmd;
+
+ /* Execute the DMA chain. */
+ mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
+#endif
+
return (void *)&panel;
}
diff --git a/drivers/video/s6e8ax0.c b/drivers/video/s6e8ax0.c
index fc09252..0e97f51 100644
--- a/drivers/video/s6e8ax0.c
+++ b/drivers/video/s6e8ax0.c
@@ -34,11 +34,11 @@
if (reverse) {
ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
- (unsigned int)data_to_send_reverse,
+ data_to_send_reverse,
ARRAY_SIZE(data_to_send_reverse));
} else {
ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
- (unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
+ data_to_send, ARRAY_SIZE(data_to_send));
}
}
@@ -50,8 +50,7 @@
};
ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
- (unsigned int)data_to_send,
- ARRAY_SIZE(data_to_send));
+ data_to_send, ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_gamma_cond(struct mipi_dsim_device *dsim_dev)
@@ -65,15 +64,18 @@
};
ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
- (unsigned int)data_to_send,
- ARRAY_SIZE(data_to_send));
+ data_to_send, ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_gamma_update(struct mipi_dsim_device *dsim_dev)
{
struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
+ static const unsigned char data_to_send[] = {
+ 0xf7, 0x03
+ };
- ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0xf7, 0x3);
+ ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, data_to_send,
+ ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_etc_source_control(struct mipi_dsim_device *dsim_dev)
@@ -84,8 +86,7 @@
};
ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
- (unsigned int)data_to_send,
- ARRAY_SIZE(data_to_send));
+ data_to_send, ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_etc_pentile_control(struct mipi_dsim_device *dsim_dev)
@@ -97,8 +98,7 @@
};
ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
- (unsigned int)data_to_send,
- ARRAY_SIZE(data_to_send));
+ data_to_send, ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_etc_mipi_control1(struct mipi_dsim_device *dsim_dev)
@@ -109,8 +109,7 @@
};
ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
- (unsigned int)data_to_send,
- ARRAY_SIZE(data_to_send));
+ data_to_send, ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_etc_mipi_control2(struct mipi_dsim_device *dsim_dev)
@@ -121,8 +120,7 @@
};
ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
- (unsigned int)data_to_send,
- ARRAY_SIZE(data_to_send));
+ data_to_send, ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_etc_power_control(struct mipi_dsim_device *dsim_dev)
@@ -133,14 +131,18 @@
};
ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
- (unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
+ data_to_send, ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_etc_mipi_control3(struct mipi_dsim_device *dsim_dev)
{
struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
+ static const unsigned char data_to_send[] = {
+ 0xe3, 0x40
+ };
- ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0xe3, 0x40);
+ ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, data_to_send,
+ ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_etc_mipi_control4(struct mipi_dsim_device *dsim_dev)
@@ -151,7 +153,7 @@
};
ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
- (unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
+ data_to_send, ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_elvss_set(struct mipi_dsim_device *dsim_dev)
@@ -162,24 +164,29 @@
};
ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
- (unsigned int)data_to_send,
- ARRAY_SIZE(data_to_send));
+ data_to_send, ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_display_on(struct mipi_dsim_device *dsim_dev)
{
struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
+ static const unsigned char data_to_send[] = {
+ 0x29, 0x00
+ };
- ops->cmd_write(dsim_dev,
- MIPI_DSI_DCS_SHORT_WRITE, 0x29, 0x00);
+ ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE, data_to_send,
+ ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_sleep_out(struct mipi_dsim_device *dsim_dev)
{
struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
+ static const unsigned char data_to_send[] = {
+ 0x11, 0x00
+ };
- ops->cmd_write(dsim_dev,
- MIPI_DSI_DCS_SHORT_WRITE, 0x11, 0x00);
+ ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE, data_to_send,
+ ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_apply_level1_key(struct mipi_dsim_device *dsim_dev)
@@ -190,7 +197,7 @@
};
ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
- (unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
+ data_to_send, ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_apply_mtp_key(struct mipi_dsim_device *dsim_dev)
@@ -201,7 +208,7 @@
};
ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
- (unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
+ data_to_send, ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_panel_init(struct mipi_dsim_device *dsim_dev)
diff --git a/drivers/video/sed156x.c b/drivers/video/sed156x.c
index d8b0d7f..f324354 100644
--- a/drivers/video/sed156x.c
+++ b/drivers/video/sed156x.c
@@ -25,7 +25,6 @@
/* include the font data */
#include <video_font.h>
-#include <video_font_data.h>
#if VIDEO_FONT_WIDTH != 8 || VIDEO_FONT_HEIGHT != 16
#error Expecting VIDEO_FONT_WIDTH == 8 && VIDEO_FONT_HEIGHT == 16
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 0904343..2f0bc6b 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -33,7 +33,6 @@
#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
-#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_MP /* support multiple processors */
#ifndef CONFIG_SYS_TEXT_BASE
@@ -75,6 +74,13 @@
#define VSC3308_TX_ADDRESS 0x02
#define VSC3308_RX_ADDRESS 0x03
+/* IDT clock synthesizers */
+#define CONFIG_IDT8T49N222A
+#define I2C_CH_IDT 0x9
+
+#define IDT_SERDES1_ADDRESS 0x6E
+#define IDT_SERDES2_ADDRESS 0x6C
+
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_SYS_NO_FLASH
@@ -578,6 +584,8 @@
#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_RMAN
+
/* Default address of microcode for the Linux Fman driver */
#if defined(CONFIG_SPIFLASH)
/*
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index 1ab6891..03f3a4f 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -224,6 +224,10 @@
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
+/* DSP CCSRBAR */
+#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+
/*
* IFC Definitions
*/
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
new file mode 100644
index 0000000..83779ef
--- /dev/null
+++ b/include/configs/C29XPCIE.h
@@ -0,0 +1,456 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * C29XPCIE board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_PHYS_64BIT
+
+#ifdef CONFIG_C29XPCIE
+#define CONFIG_PPC_C29X
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH
+#define CONFIG_SYS_TEXT_BASE 0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE /* BOOKE */
+#define CONFIG_E500 /* BOOKE e500 family */
+#define CONFIG_MPC85xx
+#define CONFIG_FSL_IFC /* Enable IFC Support */
+#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
+
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#ifdef CONFIG_PCI
+#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+
+#define CONFIG_E1000
+
+/*
+ * PCI Windows
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME "Slot 1"
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
+
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_TSEC_ENET
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_DDR_CLK_FREQ 100000000
+#define CONFIG_SYS_CLK_FREQ 66666666
+
+#define CONFIG_HWCONFIG
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+
+#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP 1
+#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START 0x00200000
+#define CONFIG_SYS_MEMTEST_END 0x00400000
+#define CONFIG_PANIC_HANG
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR3
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS 0x50
+#define CONFIG_SYS_DDR_RAW_TIMING
+
+/* DDR ECC Setup*/
+#define CONFIG_DDR_ECC
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+
+#define CONFIG_SYS_SDRAM_SIZE 512
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
+
+#define CONFIG_SYS_CCSRBAR 0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+
+/* Platform SRAM setting */
+#define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000
+#define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
+ (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
+#define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
+
+/*
+ * IFC Definitions
+ */
+/* NOR Flash on IFC */
+#define CONFIG_SYS_FLASH_BASE 0xec000000
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
+
+#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */
+
+/* 16Bit NOR Flash - S29GL512S10TFI01 */
+#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024)
+#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
+ FTIM0_NOR_TEADC(0x5) | \
+ FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1e) | \
+ FTIM1_NOR_TRAD_NOR(0x0f) | \
+ FTIM1_NOR_TSEQRAD_NOR(0x0f))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
+ FTIM2_NOR_TCH(0x4) | \
+ FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3 0x0
+
+/* CFI for NOR Flash */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE 0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
+
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+
+/* 8Bit NAND Flash - K9F1G08U0B */
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_NAND \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
+ | CSOR_NAND_PGS_2K /* Page Size = 2k */ \
+ | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
+ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \
+ FTIM0_NAND_TWP(0x0c) | \
+ FTIM0_NAND_TWCHT(0x08) | \
+ FTIM0_NAND_TWH(0x06))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \
+ FTIM1_NAND_TWBE(0x1d) | \
+ FTIM1_NAND_TRR(0x08) | \
+ FTIM1_NAND_TRP(0x0c))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \
+ FTIM2_NAND_TREH(0x0a) | \
+ FTIM2_NAND_TWHRE(0x18))
+#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04))
+
+#define CONFIG_SYS_NAND_DDR_LAW 11
+
+/* Set up IFC registers for boot location NOR/NAND */
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+
+/* CPLD on IFC, selected by CS2 */
+#define CONFIG_SYS_CPLD_BASE 0xffdf0000
+#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \
+ | CONFIG_SYS_CPLD_BASE)
+
+#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_GPCM \
+ | CSPR_V)
+#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR2 0x0
+/* CPLD Timing parameters for IFC CS2 */
+#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+ FTIM0_GPCM_TEADC(0x0e) | \
+ FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
+ FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+ FTIM2_GPCM_TCH(0x0) | \
+ FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS2_FTIM3 0x0
+
+#if defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
+#define CONFIG_SYS_INIT_RAM_END 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
+ - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+
+#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+
+/* I2C EEPROM */
+/* enable read and write access to EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+#define CONFIG_CMD_I2C
+
+/* eSPI - Enhanced SPI */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_EON
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED 10000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+
+#ifdef CONFIG_TSEC_ENET
+#define CONFIG_NET_MULTI
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC2"
+
+/* Default mode is RGMII mode */
+#define TSEC1_PHY_ADDR 0
+#define TSEC2_PHY_ADDR 2
+
+#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+
+#define CONFIG_ETHPRIME "eTSEC1"
+
+#define CONFIG_PHY_GIGE
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 10000000
+#define CONFIG_ENV_SPI_MODE 0
+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#define CONFIG_ENV_SIZE 0x2000
+#endif
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+#define CONFIG_ENV_ADDR 0xfff80000
+#else
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#endif
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#endif
+
+#define CONFIG_LOADS_ECHO
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+ /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ 1000 /* dec freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+
+#ifdef CONFIG_TSEC_ENET
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_ROOTPATH "/opt/nfsroot"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
+ "netdev=eth0\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "loadaddr=1000000\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=rootfs.ext2.gz.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=name/of/device-tree.dtb\0" \
+ "othbootargs=ramdisk_size=600000\0" \
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs; " \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 9814ca2..905bacf 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -37,7 +37,6 @@
#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
-#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_MP /* support multiple processors */
#ifndef CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/T4240EMU.h b/include/configs/T4240EMU.h
new file mode 100644
index 0000000..9fa6b77
--- /dev/null
+++ b/include/configs/T4240EMU.h
@@ -0,0 +1,170 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * T4240 EMU board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_T4240EMU
+#define CONFIG_PHYS_64BIT
+
+#define CONFIG_SYS_NO_FLASH 1
+#define CONFIG_SYS_FSL_DDR_EMU 1
+#define CONFIG_SYS_FSL_NO_QIXIS 1
+#define CONFIG_SYS_FSL_NO_SERDES 1
+
+#include "t4qds.h"
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CACHE_FLUSH
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE 0x2000
+
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_DDR_CLK_FREQ 133333333
+#define CONFIG_FSL_TBCLK_EXTRA_DIV 100
+
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SPD_BUS_NUM 1
+#define SPD_EEPROM_ADDRESS1 0x51
+#define SPD_EEPROM_ADDRESS2 0x52
+#define SPD_EEPROM_ADDRESS3 0x53
+#define SPD_EEPROM_ADDRESS4 0x54
+#define SPD_EEPROM_ADDRESS5 0x55
+#define SPD_EEPROM_ADDRESS6 0x56
+#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
+#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000) | \
+ CSPR_PORT_SIZE_32 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(0)
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
+ FTIM0_NOR_TEADC(0x1) | \
+ FTIM0_NOR_TEAHC(0x1))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
+ FTIM1_NOR_TRAD_NOR(0x1))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
+ FTIM2_NOR_TCH(0x0) | \
+ FTIM2_NOR_TWP(0x1))
+#define CONFIG_SYS_NOR_FTIM3 0x04000000
+#define CONFIG_SYS_IFC_CCR 0x01000000
+
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+
+
+/* I2C */
+#define CONFIG_SYS_FSL_I2C_SPEED 4000000 /* faster speed for emulator */
+#define CONFIG_SYS_FSL_I2C2_SPEED 4000000
+
+/* Qman/Bman */
+#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS 50
+#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS 50
+#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+#define CONFIG_SYS_PMAN
+#define CONFIG_SYS_DPAA_DCE
+#define CONFIG_SYS_DPAA_RMAN
+#define CONFIG_SYS_INTERLAKEN
+
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+
+
+
+#define CONFIG_BOOTDELAY 0
+
+/*
+ * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
+ * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
+ * interleaving. It can be cacheline, page, bank, superbank.
+ * See doc/README.fsl-ddr for details.
+ */
+#ifdef CONFIG_PPC_T4240
+#define CTRL_INTLV_PREFERED 3way_4KB
+#else
+#define CTRL_INTLV_PREFERED cacheline
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:" \
+ "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
+ "bank_intlv=auto;" \
+ "netdev=eth0\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=t4240emu/ramdisk.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=t4240emu/t4240emu.dtb\0" \
+ "bdev=sda3\0" \
+ "c=ffe\0"
+
+/*
+ * For emulation this causes u-boot to jump to the start of the proof point
+ * app code automatically
+ */
+#define CONFIG_PROOF_POINTS \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "cpu 1 release 0x29000000 - - -;" \
+ "cpu 2 release 0x29000000 - - -;" \
+ "cpu 3 release 0x29000000 - - -;" \
+ "cpu 4 release 0x29000000 - - -;" \
+ "cpu 5 release 0x29000000 - - -;" \
+ "cpu 6 release 0x29000000 - - -;" \
+ "cpu 7 release 0x29000000 - - -;" \
+ "go 0x29000000"
+
+#define CONFIG_HVBOOT \
+ "setenv bootargs config-addr=0x60000000; " \
+ "bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_LINUX \
+ "errata;" \
+ "setenv othbootargs ignore_loglevel;" \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "setenv ramdiskaddr 0x02000000;" \
+ "setenv fdtaddr 0x00c00000;" \
+ "setenv loadaddr 0x1000000;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_LINUX
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index 9ac7f69..92a30ab 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -7,6 +7,9 @@
/*
* T4240 QDS board configuration file
*/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
#define CONFIG_T4240QDS
#define CONFIG_PHYS_64BIT
@@ -15,4 +18,543 @@
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg
+#endif
+
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+#define CONFIG_DDR_ECC
+
#include "t4qds.h"
+
+#ifdef CONFIG_SYS_NO_FLASH
+#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 10000000
+#define CONFIG_ENV_SPI_MODE 0
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET (512 * 1097)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR 0xffe20000
+#define CONFIG_ENV_SIZE 0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE 0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS1 0x51
+#define SPD_EEPROM_ADDRESS2 0x52
+#define SPD_EEPROM_ADDRESS3 0x53
+#define SPD_EEPROM_ADDRESS4 0x54
+#define SPD_EEPROM_ADDRESS5 0x55
+#define SPD_EEPROM_ADDRESS6 0x56
+#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
+#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
+#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
+#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
+
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
+ FTIM0_NOR_TEADC(0x5) | \
+ FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
+ FTIM1_NOR_TRAD_NOR(0x1A) |\
+ FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
+ FTIM2_NOR_TCH(0x4) | \
+ FTIM2_NOR_TWPH(0x0E) | \
+ FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3 0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+
+#define CONFIG_FSL_QIXIS /* use common QIXIS code */
+#define QIXIS_BASE 0xffdf0000
+#define QIXIS_LBMAP_SWITCH 6
+#define QIXIS_LBMAP_MASK 0x0f
+#define QIXIS_LBMAP_SHIFT 0
+#define QIXIS_LBMAP_DFLTBANK 0x00
+#define QIXIS_LBMAP_ALTBANK 0x04
+#define QIXIS_RST_CTL_RESET 0x83
+#define QIXIS_RST_FORCE_MEM 0x1
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
+
+#define CONFIG_SYS_CSPR3_EXT (0xf)
+#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_GPCM \
+ | CSPR_V)
+#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
+#define CONFIG_SYS_CSOR3 0x0
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+ FTIM0_GPCM_TEADC(0x0e) | \
+ FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
+ FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+ FTIM2_GPCM_TCH(0x0) | \
+ FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS3_FTIM3 0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE 0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+ | CSPR_MSEL_NAND /* MSEL = NAND */ \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
+ | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
+ | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+ FTIM0_NAND_TWP(0x18) | \
+ FTIM0_NAND_TWCHT(0x07) | \
+ FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+ FTIM1_NAND_TWBE(0x39) | \
+ FTIM1_NAND_TRR(0x0e) | \
+ FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+ FTIM2_NAND_TREH(0x0a) | \
+ FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3 0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW 11
+
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#endif
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+
+/* I2C */
+#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
+#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
+#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
+#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
+
+#define I2C_MUX_CH_DEFAULT 0x8
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+#define I2C_MUX_CH_VSC3316_FS 0xc
+#define I2C_MUX_CH_VSC3316_BS 0xd
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR 0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+
+/* VSC Crossbar switches */
+#define CONFIG_VSC_CROSSBAR
+#define VSC3316_FSM_TX_ADDR 0x70
+#define VSC3316_FSM_RX_ADDR 0x71
+
+/*
+ * RapidIO
+ */
+
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED 10000000
+#define CONFIG_SF_DEFAULT_MODE 0
+
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS 50
+#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS 50
+#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+#define CONFIG_SYS_PMAN
+#define CONFIG_SYS_DPAA_DCE
+#define CONFIG_SYS_DPAA_RMAN
+#define CONFIG_SYS_INTERLAKEN
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 545KB (1089 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_TERANETICS
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+#define FM1_10GEC1_PHY_ADDR 0x0
+#define FM1_10GEC2_PHY_ADDR 0x1
+#define FM2_10GEC1_PHY_ADDR 0x2
+#define FM2_10GEC2_PHY_ADDR 0x3
+#endif
+
+
+/* SATA */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_ETHPRIME "FM1@DTSEC1"
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#define CONFIG_HAS_FSL_DR_USB
+
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+
+#define __USB_PHY_TYPE utmi
+
+/*
+ * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
+ * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
+ * interleaving. It can be cacheline, page, bank, superbank.
+ * See doc/README.fsl-ddr for details.
+ */
+#ifdef CONFIG_PPC_T4240
+#define CTRL_INTLV_PREFERED 3way_4KB
+#else
+#define CTRL_INTLV_PREFERED cacheline
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:" \
+ "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
+ "bank_intlv=auto;" \
+ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+ "netdev=eth0\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot && " \
+ "protect off $ubootaddr +$filesize && " \
+ "erase $ubootaddr +$filesize && " \
+ "cp.b $loadaddr $ubootaddr $filesize && " \
+ "protect on $ubootaddr +$filesize && " \
+ "cmp.b $loadaddr $ubootaddr $filesize\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=t4240qds/ramdisk.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=t4240qds/t4240qds.dtb\0" \
+ "bdev=sda3\0" \
+ "c=ffe\0"
+
+#define CONFIG_HVBOOT \
+ "setenv bootargs config-addr=0x60000000; " \
+ "bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_ALU \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "cpu 1 release 0x01000000 - - -;" \
+ "cpu 2 release 0x01000000 - - -;" \
+ "cpu 3 release 0x01000000 - - -;" \
+ "cpu 4 release 0x01000000 - - -;" \
+ "cpu 5 release 0x01000000 - - -;" \
+ "cpu 6 release 0x01000000 - - -;" \
+ "cpu 7 release 0x01000000 - - -;" \
+ "go 0x01000000"
+
+#define CONFIG_LINUX \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "setenv ramdiskaddr 0x02000000;" \
+ "setenv fdtaddr 0x00c00000;" \
+ "setenv loadaddr 0x1000000;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_LINUX
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index c0591c5..c3fb80c 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -42,7 +42,6 @@
#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
-#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_MP /* support multiple processors */
#ifndef CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 1b0be23..9657228 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -34,7 +34,7 @@
#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
-#if defined(CONFIG_P1020RDB)
+#if defined(CONFIG_P1020RDB_PC)
#define CONFIG_BOARDNAME "P1020RDB-PC"
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_P1020
@@ -50,6 +50,35 @@
#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
+/*
+ * P1020RDB-PD board has user selectable switches for evaluating different
+ * frequency and boot options for the P1020 device. The table that
+ * follow describe the available options. The front six binary number was in
+ * accordance with SW3[1:6].
+ * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
+ * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
+ * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
+ * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
+ * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
+ * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
+ * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
+ */
+#if defined(CONFIG_P1020RDB_PD)
+#define CONFIG_BOARDNAME "P1020RDB-PD"
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_P1020
+#define CONFIG_SPI_FLASH
+#define CONFIG_VSC7385_ENET
+#define CONFIG_SLIC
+#define __SW_BOOT_MASK 0x03
+#define __SW_BOOT_NOR 0x64
+#define __SW_BOOT_SPI 0x34
+#define __SW_BOOT_SD 0x24
+#define __SW_BOOT_NAND 0x44
+#define __SW_BOOT_PCIE 0x74
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#endif
+
#if defined(CONFIG_P1021RDB)
#define CONFIG_BOARDNAME "P1021RDB-PC"
#define CONFIG_NAND_FSL_ELBC
@@ -259,7 +288,7 @@
#define SPD_EEPROM_ADDRESS 0x52
#undef CONFIG_FSL_DDR_INTERACTIVE
-#ifdef CONFIG_P1020MBG
+#if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
#else
@@ -330,7 +359,7 @@
/*
* Local Bus Definitions
*/
-#if defined(CONFIG_P1020MBG)
+#if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
#define CONFIG_SYS_FLASH_BASE 0xec000000
#elif defined(CONFIG_P1020UTM)
@@ -381,13 +410,27 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
+#if defined(CONFIG_P1020RDB_PD)
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#else
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
+#endif
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
+#if defined(CONFIG_P1020RDB_PD)
+#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
+ | OR_FCM_PGS /* Large Page*/ \
+ | OR_FCM_CSCT \
+ | OR_FCM_CST \
+ | OR_FCM_CHT \
+ | OR_FCM_SCY_1 \
+ | OR_FCM_TRLX \
+ | OR_FCM_EHTR)
+#else
#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
| OR_FCM_CSCT \
| OR_FCM_CST \
@@ -395,6 +438,7 @@
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
| OR_FCM_EHTR)
+#endif
#endif /* CONFIG_NAND_FSL_ELBC */
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
new file mode 100644
index 0000000..4aa7064
--- /dev/null
+++ b/include/configs/p1_twr.h
@@ -0,0 +1,619 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * QorIQ P1 Tower boards configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if defined(CONFIG_TWR_P1025)
+#define CONFIG_BOARDNAME "TWR-P1025"
+#define CONFIG_P1025
+#define CONFIG_PHY_ATHEROS
+#define CONFIG_QE
+#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */
+#define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */
+#endif
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RAMBOOT_SDCARD
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_SYS_TEXT_BASE 0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500
+#define CONFIG_MPC85xx
+
+#define CONFIG_MP
+
+#define CONFIG_FSL_ELBC
+#define CONFIG_PCI
+#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
+#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+
+#define CONFIG_FSL_LAW
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_CMD_SATA
+#define CONFIG_SATA_SIL3114
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_LIBATA
+#define CONFIG_LBA48
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */
+
+#define CONFIG_DDR_CLK_FREQ 66666666
+
+#define CONFIG_HWCONFIG
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE
+#define CONFIG_BTB
+
+#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
+
+#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x1fffffff
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+
+#define CONFIG_SYS_CCSRBAR 0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR3
+
+#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
+
+#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+
+/* Default settings for DDR3 */
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
+#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
+#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
+#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
+#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
+#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
+
+#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
+#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
+#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
+
+#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608
+#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
+#define CONFIG_SYS_DDR_RCW_1 0x00000000
+#define CONFIG_SYS_DDR_RCW_2 0x00000000
+#define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */
+#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
+#define CONFIG_SYS_DDR_TIMING_4 0x00220001
+#define CONFIG_SYS_DDR_TIMING_5 0x03402400
+
+#define CONFIG_SYS_DDR_TIMING_3 0x00020000
+#define CONFIG_SYS_DDR_TIMING_0 0x00220004
+#define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544
+#define CONFIG_SYS_DDR_TIMING_2 0x0fa880de
+#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
+#define CONFIG_SYS_DDR_MODE_1 0x80461320
+#define CONFIG_SYS_DDR_MODE_2 0x00008000
+#define CONFIG_SYS_DDR_INTERVAL 0x09480000
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable
+ * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
+ * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
+ *
+ * Localbus
+ * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable
+ * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable
+ *
+ * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable
+ * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable
+ * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
+#define CONFIG_SYS_FLASH_BASE 0xec000000
+
+#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
+ | BR_PS_16 | BR_V)
+
+#define CONFIG_FLASH_OR_PRELIM 0xfc0000b1
+
+#define CONFIG_SYS_SSD_BASE 0xe0000000
+#define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE
+#define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \
+ BR_PS_16 | BR_V)
+#define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
+ OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \
+ OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
+
+#define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM
+#define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM
+
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
+/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+/* Size of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)/* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
+
+#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
+
+/* Serial Port
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+#define CONFIG_SYS_64BIT_STRTOUL
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
+#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+
+#define CONFIG_SYS_I2C_PCA9555_ADDR 0x23
+
+/* enable read and write access to EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_HARD_SPI
+#define CONFIG_FSL_ESPI
+
+#if defined(CONFIG_PCI)
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 2, direct to uli, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT"
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI
+#endif
+
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#undef CONFIG_TSEC2
+#undef CONFIG_TSEC2_NAME
+#define CONFIG_TSEC3
+#define CONFIG_TSEC3_NAME "eTSEC3"
+
+#define TSEC1_PHY_ADDR 2
+#define TSEC2_PHY_ADDR 0
+#define TSEC3_PHY_ADDR 1
+
+#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define TSEC3_PHYIDX 0
+
+#define CONFIG_ETHPRIME "eTSEC1"
+
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#undef CONFIG_HAS_ETH2
+#endif /* CONFIG_TSEC_ENET */
+
+#ifdef CONFIG_QE
+/* QE microcode/firmware address */
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#endif /* CONFIG_QE */
+
+#ifdef CONFIG_TWR_P1025
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
+
+#undef CONFIG_UEC_ETH
+#define CONFIG_PHY_MODE_NEED_CHANGE
+
+#define CONFIG_UEC_ETH1 /* ETH1 */
+#define CONFIG_HAS_ETH0
+
+#ifdef CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
+#define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
+#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
+#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
+#endif /* CONFIG_UEC_ETH1 */
+
+#define CONFIG_UEC_ETH5 /* ETH5 */
+#define CONFIG_HAS_ETH1
+
+#ifdef CONFIG_UEC_ETH5
+#define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
+#define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
+#define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
+#define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */
+#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
+#endif /* CONFIG_UEC_ETH5 */
+#endif /* CONFIG_TWR-P1025 */
+
+/*
+ * Environment
+ */
+#ifdef CONFIG_SYS_RAMBOOT
+#ifdef CONFIG_RAMBOOT_SDCARD
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#else
+#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE 0x2000
+#endif
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+#define CONFIG_ENV_ADDR 0xfff80000
+#else
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#endif
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+
+#if defined(CONFIG_HAS_FSL_DR_USB)
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#endif
+#endif
+
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#endif
+
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
+ || defined(CONFIG_FSL_SATA)
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+ /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_HOSTNAME unknown
+#define CONFIG_ROOTPATH "/opt/nfsroot"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#define CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+"netdev=eth0\0" \
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+"loadaddr=1000000\0" \
+"bootfile=uImage\0" \
+"dtbfile=twr-p1025twr.dtb\0" \
+"ramdiskfile=rootfs.ext2.gz.uboot\0" \
+"qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \
+"tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+"kernelflash=tftpboot $loadaddr $bootfile; " \
+ "protect off 0xefa80000 +$filesize; " \
+ "erase 0xefa80000 +$filesize; " \
+ "cp.b $loadaddr 0xefa80000 $filesize; " \
+ "protect on 0xefa80000 +$filesize; " \
+ "cmp.b $loadaddr 0xefa80000 $filesize\0" \
+"dtbflash=tftpboot $loadaddr $dtbfile; " \
+ "protect off 0xefe80000 +$filesize; " \
+ "erase 0xefe80000 +$filesize; " \
+ "cp.b $loadaddr 0xefe80000 $filesize; " \
+ "protect on 0xefe80000 +$filesize; " \
+ "cmp.b $loadaddr 0xefe80000 $filesize\0" \
+"ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \
+ "protect off 0xeeb80000 +$filesize; " \
+ "erase 0xeeb80000 +$filesize; " \
+ "cp.b $loadaddr 0xeeb80000 $filesize; " \
+ "protect on 0xeeb80000 +$filesize; " \
+ "cmp.b $loadaddr 0xeeb80000 $filesize\0" \
+"qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \
+ "protect off 0xefec0000 +$filesize; " \
+ "erase 0xefec0000 +$filesize; " \
+ "cp.b $loadaddr 0xefec0000 $filesize; " \
+ "protect on 0xefec0000 +$filesize; " \
+ "cmp.b $loadaddr 0xefec0000 $filesize\0" \
+"consoledev=ttyS0\0" \
+"ramdiskaddr=2000000\0" \
+"ramdiskfile=rootfs.ext2.gz.uboot\0" \
+"fdtaddr=c00000\0" \
+"bdev=sda1\0" \
+"norbootaddr=ef080000\0" \
+"norfdtaddr=ef040000\0" \
+"ramdisk_size=120000\0" \
+"usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \
+"console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000"
+
+#define CONFIG_NFSBOOTCOMMAND \
+"setenv bootargs root=/dev/nfs rw " \
+"nfsroot=$serverip:$rootpath " \
+"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+"console=$consoledev,$baudrate $othbootargs;" \
+"tftp $loadaddr $bootfile&&" \
+"tftp $fdtaddr $fdtfile&&" \
+"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_HDBOOT \
+"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
+"console=$consoledev,$baudrate $othbootargs;" \
+"usb start;" \
+"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
+"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
+"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_USB_FAT_BOOT \
+"setenv bootargs root=/dev/ram rw " \
+"console=$consoledev,$baudrate $othbootargs " \
+"ramdisk_size=$ramdisk_size;" \
+"usb start;" \
+"fatload usb 0:2 $loadaddr $bootfile;" \
+"fatload usb 0:2 $fdtaddr $fdtfile;" \
+"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
+"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_USB_EXT2_BOOT \
+"setenv bootargs root=/dev/ram rw " \
+"console=$consoledev,$baudrate $othbootargs " \
+"ramdisk_size=$ramdisk_size;" \
+"usb start;" \
+"ext2load usb 0:4 $loadaddr $bootfile;" \
+"ext2load usb 0:4 $fdtaddr $fdtfile;" \
+"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
+"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_NORBOOT \
+"setenv bootargs root=/dev/mtdblock3 rw " \
+"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
+"bootm $norbootaddr - $norfdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND_TFTP \
+"setenv bootargs root=/dev/ram rw " \
+"console=$consoledev,$baudrate $othbootargs " \
+"ramdisk_size=$ramdisk_size;" \
+"tftp $ramdiskaddr $ramdiskfile;" \
+"tftp $loadaddr $bootfile;" \
+"tftp $fdtaddr $fdtfile;" \
+"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+"setenv bootargs root=/dev/ram rw " \
+"console=$consoledev,$baudrate $othbootargs " \
+"ramdisk_size=$ramdisk_size;" \
+"bootm 0xefa80000 0xeeb80000 0xefe80000"
+
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index 1ed53db..3e82fc2 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -7,24 +7,8 @@
/*
* Corenet DS style board configuration file
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg
-#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg
-#endif
-
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-/* Set 1M boot space */
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_SYS_NO_FLASH
-#endif
+#ifndef __T4QDS_H
+#define __T4QDS_H
#define CONFIG_CMD_REGINFO
@@ -34,7 +18,6 @@
#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
-#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_MP /* support multiple processors */
#ifndef CONFIG_SYS_TEXT_BASE
@@ -58,70 +41,16 @@
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
-#ifdef CONFIG_SYS_NO_FLASH
-#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_ENV_IS_NOWHERE
-#endif
-#else
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#endif
-
-#if defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SPI_BUS 0
-#define CONFIG_ENV_SPI_CS 0
-#define CONFIG_ENV_SPI_MAX_HZ 10000000
-#define CONFIG_ENV_SPI_MODE 0
-#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
-#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#elif defined(CONFIG_SDCARD)
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_OFFSET (512 * 1097)
-#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-#define CONFIG_ENV_IS_IN_REMOTE
-#define CONFIG_ENV_ADDR 0xffe20000
-#define CONFIG_ENV_SIZE 0x2000
-#elif defined(CONFIG_ENV_IS_NOWHERE)
-#define CONFIG_ENV_SIZE 0x2000
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
-#endif
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
-#endif
-
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
@@ -129,14 +58,9 @@
#define CONFIG_ENABLE_36BIT_PHYS
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_ADDR_MAP
#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-#if 0
-#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
-#endif
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
#define CONFIG_SYS_ALT_MEMTEST
@@ -147,17 +71,8 @@
*/
#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_DCSRBAR 0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
-#endif
-
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
/*
* DDR Setup
@@ -174,199 +89,16 @@
#define CONFIG_DDR_SPD
#define CONFIG_FSL_DDR3
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS1 0x51
-#define SPD_EEPROM_ADDRESS2 0x52
-#define SPD_EEPROM_ADDRESS3 0x53
-#define SPD_EEPROM_ADDRESS4 0x54
-#define SPD_EEPROM_ADDRESS5 0x55
-#define SPD_EEPROM_ADDRESS6 0x56
-#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
/*
* IFC Definitions
*/
#define CONFIG_SYS_FLASH_BASE 0xe0000000
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#endif
-#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-/* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
-
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
- FTIM0_NOR_TEADC(0x5) | \
- FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
- FTIM1_NOR_TRAD_NOR(0x1A) |\
- FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
- FTIM2_NOR_TCH(0x4) | \
- FTIM2_NOR_TWPH(0x0E) | \
- FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3 0x0
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
-
-#define CONFIG_FSL_QIXIS /* use common QIXIS code */
-#define QIXIS_BASE 0xffdf0000
-#define QIXIS_LBMAP_SWITCH 6
-#define QIXIS_LBMAP_MASK 0x0f
-#define QIXIS_LBMAP_SHIFT 0
-#define QIXIS_LBMAP_DFLTBANK 0x00
-#define QIXIS_LBMAP_ALTBANK 0x04
-#define QIXIS_RST_CTL_RESET 0x83
-#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
-#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
-#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
-#ifdef CONFIG_PHYS_64BIT
-#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
-#else
-#define QIXIS_BASE_PHYS QIXIS_BASE
-#endif
-
-#define CONFIG_SYS_CSPR3_EXT (0xf)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_GPCM \
- | CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024)
-#define CONFIG_SYS_CSOR3 0x0
-/* QIXIS Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
- FTIM0_GPCM_TEADC(0x0e) | \
- FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
- FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x0) | \
- FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3 0x0
-
-/* NAND Flash on IFC */
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-
-#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
- | CSPR_MSEL_NAND /* MSEL = NAND */ \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
- | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
- | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
- | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
- FTIM0_NAND_TWP(0x18) | \
- FTIM0_NAND_TWCHT(0x07) | \
- FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
- FTIM1_NAND_TWBE(0x39) | \
- FTIM1_NAND_TRR(0x0e) | \
- FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
- FTIM2_NAND_TREH(0x0a) | \
- FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
-
-#define CONFIG_SYS_NAND_DDR_LAW 11
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_CMD_NAND
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-#if defined(CONFIG_NAND)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
-#endif
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
#define CONFIG_MISC_INIT_R
@@ -376,18 +108,12 @@
#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
/* The assembler doesn't like typecast */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
-#endif
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
@@ -431,149 +157,55 @@
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 100000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_SPEED 100000
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
-#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
-#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
-
-#define I2C_MUX_CH_DEFAULT 0x8
-#define I2C_MUX_CH_VOL_MONITOR 0xa
-#define I2C_MUX_CH_VSC3316_FS 0xc
-#define I2C_MUX_CH_VSC3316_BS 0xd
-
-/* Voltage monitor on channel 2*/
-#define I2C_VOL_MONITOR_ADDR 0x40
-#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
-#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
-#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
-
-/* VSC Crossbar switches */
-#define CONFIG_VSC_CROSSBAR
-#define VSC3316_FSM_TX_ADDR 0x70
-#define VSC3316_FSM_RX_ADDR 0x71
-
/*
* RapidIO
*/
#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
-#endif
#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
-#else
-#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
-#endif
#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
/*
- * for slave u-boot IMAGE instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
-/*
- * for slave UCODE and ENV instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
-
-/* slave core release by master*/
-#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
-
-/*
- * SRIO_PCIE_BOOT - SLAVE
- */
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
-#endif
-/*
- * eSPI - Enhanced SPI
- */
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_CMD_SF
-#define CONFIG_SF_DEFAULT_SPEED 10000000
-#define CONFIG_SF_DEFAULT_MODE 0
-
-/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
-#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
-#endif
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
-#endif
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
-#endif
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
-#else
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
-#endif
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
-#else
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
-#endif
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* controller 4, Base address 203000 */
@@ -584,84 +216,6 @@
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
-/* Qman/Bman */
-#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
-#define CONFIG_SYS_BMAN_NUM_PORTALS 50
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#else
-#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
-#endif
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_NUM_PORTALS 50
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#else
-#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
-#endif
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-#define CONFIG_SYS_PMAN
-#define CONFIG_SYS_DPAA_DCE
-#define CONFIG_SYS_INTERLAKEN
-
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 545KB (1089 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
- */
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
-#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-/*
- * Slave has no ucode locally, it can fetch this from remote. When implementing
- * in two corenet boards, slave's ucode could be stored in master's memory
- * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO or PCIE outbound window->master inbound window->
- * master LAW->the ucode address in master's memory space.
- */
-#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
-#else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-#endif /* CONFIG_NOBQFMAN */
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
-#define CONFIG_PHYLIB_10G
-#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_TERANETICS
-#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
-#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
-#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
-#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
-#define FM1_10GEC1_PHY_ADDR 0x0
-#define FM1_10GEC2_PHY_ADDR 0x1
-#define FM2_10GEC1_PHY_ADDR 0x2
-#define FM2_10GEC2_PHY_ADDR 0x3
-#endif
-
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_NET_MULTI
@@ -724,30 +278,6 @@
#endif
/*
-* USB
-*/
-#define CONFIG_CMD_USB
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_CMD_EXT2
-#define CONFIG_HAS_FSL_DR_USB
-
-#define CONFIG_MMC
-
-#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
@@ -788,112 +318,11 @@
/* default location for tftp and bootm */
#define CONFIG_LOADADDR 1000000
-#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200
-#define __USB_PHY_TYPE utmi
-
-/*
- * T4240 has 3 DDR controllers. Default to 3way_4KB interleaving. It can be
- * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to
- * cacheline interleaving. It can be cacheline, page, bank, superbank.
- * See doc/README.fsl-ddr for details.
- */
-#ifdef CONFIG_PPC_T4240
-#define CTRL_INTLV_PREFERED 3way_4KB
-#else
-#define CTRL_INTLV_PREFERED cacheline
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:" \
- "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
- "bank_intlv=auto;" \
- "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
- "netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot && " \
- "protect off $ubootaddr +$filesize && " \
- "erase $ubootaddr +$filesize && " \
- "cp.b $loadaddr $ubootaddr $filesize && " \
- "protect on $ubootaddr +$filesize && " \
- "cmp.b $loadaddr $ubootaddr $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=t4240qds/ramdisk.uboot\0" \
- "fdtaddr=c00000\0" \
- "fdtfile=t4240qds/t4240qds.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
-
-/* For emulation this causes u-boot to jump to the start of the proof point
- app code automatically */
-#define CONFIG_PROOF_POINTS \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "cpu 1 release 0x29000000 - - -;" \
- "cpu 2 release 0x29000000 - - -;" \
- "cpu 3 release 0x29000000 - - -;" \
- "cpu 4 release 0x29000000 - - -;" \
- "cpu 5 release 0x29000000 - - -;" \
- "cpu 6 release 0x29000000 - - -;" \
- "cpu 7 release 0x29000000 - - -;" \
- "go 0x29000000"
-
#define CONFIG_HVBOOT \
"setenv bootargs config-addr=0x60000000; " \
"bootm 0x01000000 - 0x00f00000"
-#define CONFIG_ALU \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "cpu 1 release 0x01000000 - - -;" \
- "cpu 2 release 0x01000000 - - -;" \
- "cpu 3 release 0x01000000 - - -;" \
- "cpu 4 release 0x01000000 - - -;" \
- "cpu 5 release 0x01000000 - - -;" \
- "cpu 6 release 0x01000000 - - -;" \
- "cpu 7 release 0x01000000 - - -;" \
- "go 0x01000000"
-
-#define CONFIG_LINUX \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "setenv ramdiskaddr 0x02000000;" \
- "setenv fdtaddr 0x00c00000;" \
- "setenv loadaddr 0x1000000;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_LINUX
-
-#ifdef CONFIG_SECURE_BOOT
-#include <asm/fsl_secure_boot.h>
-#endif
-
#endif /* __CONFIG_H */
diff --git a/include/edid.h b/include/edid.h
index f153091..480a773 100644
--- a/include/edid.h
+++ b/include/edid.h
@@ -54,7 +54,7 @@
(_x).vertical_blanking)
unsigned char hsync_offset;
unsigned char hsync_pulse_width;
- unsigned char sync_offset_pulse_width;
+ unsigned char vsync_offset_pulse_width;
unsigned char hsync_vsync_offset_pulse_width_hi;
#define EDID_DETAILED_TIMING_HSYNC_OFFSET(_x) \
((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 7, 6) << 8) + \
diff --git a/include/pci.h b/include/pci.h
index 01002a4..911ba89 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -410,13 +410,6 @@
#define PCI_MAX_PCI_DEVICES 32
#define PCI_MAX_PCI_FUNCTIONS 8
-#define PCI_DCR 0x54 /* PCIe Device Control Register */
-#define PCI_DSR 0x56 /* PCIe Device Status Register */
-#define PCI_LSR 0x5e /* PCIe Link Status Register */
-#define PCI_LCR 0x5c /* PCIe Link Control Register */
-#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
-#define PCI_LTSSM_L0 0x16 /* L0 state */
-
/* Include the ID list */
#include <pci_ids.h>
diff --git a/include/video_font.h b/include/video_font.h
index 7ef9519..96b9edb 100644
--- a/include/video_font.h
+++ b/include/video_font.h
@@ -8,9 +8,10 @@
#ifndef _VIDEO_FONT_
#define _VIDEO_FONT_
-#define VIDEO_FONT_CHARS 256
-#define VIDEO_FONT_WIDTH 8
-#define VIDEO_FONT_HEIGHT 16
-#define VIDEO_FONT_SIZE (VIDEO_FONT_CHARS * VIDEO_FONT_HEIGHT)
+#ifdef CONFIG_VIDEO_FONT_4X6
+#include <video_font_4x6.h>
+#else
+#include <video_font_data.h>
+#endif
#endif /* _VIDEO_FONT_ */
diff --git a/include/video_font_4x6.h b/include/video_font_4x6.h
new file mode 100644
index 0000000..d1778d5
--- /dev/null
+++ b/include/video_font_4x6.h
@@ -0,0 +1,2154 @@
+
+/* Hand composed "Minuscule" 4x6 font, with binary data generated using
+ * Perl stub.
+ *
+ * Use 'perl -x mini_4x6.c < mini_4x6.c > new_version.c' to regenerate
+ * binary data.
+ *
+ * Created by Kenneth Albanowski.
+ * No rights reserved, released to the public domain.
+ *
+ * Version 1.0
+ */
+
+/*
+
+#!/usr/bin/perl -pn
+
+s{((0x)?[0-9a-fA-F]+)(.*\[([\*\ ]{4})\])}{
+
+ ($num,$pat,$bits) = ($1,$3,$4);
+
+ $bits =~ s/([^\s0])|(.)/ defined($1) + 0 /ge;
+
+ $num = ord(pack("B8", $bits));
+ $num |= $num >> 4;
+ $num = sprintf("0x%.2x", $num);
+
+ #print "$num,$pat,$bits\n";
+
+ $num . $pat;
+}ge;
+
+__END__;
+*/
+
+/* Note: binary data consists of one byte for each row of each character top
+ to bottom, character 0 to character 255, six bytes per character. Each
+ byte contains the same four character bits in both nybbles.
+ MSBit to LSBit = left to right.
+ */
+
+#ifndef _VIDEO_FONT_DATA_
+#define _VIDEO_FONT_DATA_
+
+#define VIDEO_FONT_CHARS 256
+#define VIDEO_FONT_WIDTH 4
+#define VIDEO_FONT_HEIGHT 6
+#define VIDEO_FONT_SIZE (VIDEO_FONT_CHARS * VIDEO_FONT_HEIGHT)
+
+static unsigned char video_fontdata[VIDEO_FONT_SIZE] = {
+
+ /*{*/
+ /* Char 0: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 1: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 2: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 3: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 4: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 5: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 6: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 7: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 8: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 9: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 10: '' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 11: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 12: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 13: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 14: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 15: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 16: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 17: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 18: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 19: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 20: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 21: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 22: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 23: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 24: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 25: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 26: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 27: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 28: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 29: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 30: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 31: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 32: ' ' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 33: '!' */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 34: '"' */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 35: '#' */
+ 0xaa, /*= [* * ] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 36: '$' */
+ 0x44, /*= [ * ] */
+ 0x66, /*= [ ** ] */
+ 0xee, /*= [*** ] */
+ 0xcc, /*= [** ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 37: '%' */
+ 0xaa, /*= [* * ] */
+ 0x22, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x88, /*= [* ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 38: '&' */
+ 0x66, /*= [ ** ] */
+ 0x99, /*= [* *] */
+ 0x66, /*= [ ** ] */
+ 0xaa, /*= [* * ] */
+ 0xdd, /*= [** *] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 39: ''' */
+ 0x22, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 40: '(' */
+ 0x22, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 41: ')' */
+ 0x44, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 42: '*' */
+ 0x00, /*= [ ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 43: '+' */
+ 0x00, /*= [ ] */
+ 0x44, /*= [ * ] */
+ 0xee, /*= [*** ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 44: ',' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x44, /*= [ * ] */
+ 0x88, /*= [* ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 45: '-' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 46: '.' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 47: '/' */
+ 0x00, /*= [ ] */
+ 0x22, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x88, /*= [* ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 48: '0' */
+ 0x44, /*= [ * ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 49: '1' */
+ 0x44, /*= [ * ] */
+ 0xcc, /*= [** ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 50: '2' */
+ 0xcc, /*= [** ] */
+ 0x22, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x88, /*= [* ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 51: '3' */
+ 0xee, /*= [*** ] */
+ 0x22, /*= [ * ] */
+ 0x66, /*= [ ** ] */
+ 0x22, /*= [ * ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 52: '4' */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0x22, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 53: '5' */
+ 0xee, /*= [*** ] */
+ 0x88, /*= [* ] */
+ 0xee, /*= [*** ] */
+ 0x22, /*= [ * ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 54: '6' */
+ 0xee, /*= [*** ] */
+ 0x88, /*= [* ] */
+ 0xee, /*= [*** ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 55: '7' */
+ 0xee, /*= [*** ] */
+ 0x22, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 56: '8' */
+ 0xee, /*= [*** ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 57: '9' */
+ 0xee, /*= [*** ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0x22, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 58: ':' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 59: ';' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ 0x44, /*= [ * ] */
+ 0x88, /*= [* ] */
+ /*}*/
+ /*{*/ /* Char 60: '<' */
+ 0x22, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x88, /*= [* ] */
+ 0x44, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 61: '=' */
+ 0x00, /*= [ ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 62: '>' */
+ 0x88, /*= [* ] */
+ 0x44, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x88, /*= [* ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 63: '?' */
+ 0xee, /*= [*** ] */
+ 0x22, /*= [ * ] */
+ 0x66, /*= [ ** ] */
+ 0x00, /*= [ ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 64: '@' */
+ 0x44, /*= [ * ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x88, /*= [* ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 65: 'A' */
+ 0x44, /*= [ * ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 66: 'B' */
+ 0xcc, /*= [** ] */
+ 0xaa, /*= [* * ] */
+ 0xcc, /*= [** ] */
+ 0xaa, /*= [* * ] */
+ 0xcc, /*= [** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 67: 'C' */
+ 0x66, /*= [ ** ] */
+ 0x88, /*= [* ] */
+ 0x88, /*= [* ] */
+ 0x88, /*= [* ] */
+ 0x66, /*= [ ** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 68: 'D' */
+ 0xcc, /*= [** ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0xcc, /*= [** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 69: 'E' */
+ 0xee, /*= [*** ] */
+ 0x88, /*= [* ] */
+ 0xee, /*= [*** ] */
+ 0x88, /*= [* ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 70: 'F' */
+ 0xee, /*= [*** ] */
+ 0x88, /*= [* ] */
+ 0xee, /*= [*** ] */
+ 0x88, /*= [* ] */
+ 0x88, /*= [* ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 71: 'G' */
+ 0x66, /*= [ ** ] */
+ 0x88, /*= [* ] */
+ 0xee, /*= [*** ] */
+ 0xaa, /*= [* * ] */
+ 0x66, /*= [ ** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 72: 'H' */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 73: 'I' */
+ 0xee, /*= [*** ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 74: 'J' */
+ 0x22, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0xaa, /*= [* * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 75: 'K' */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0xcc, /*= [** ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 76: 'L' */
+ 0x88, /*= [* ] */
+ 0x88, /*= [* ] */
+ 0x88, /*= [* ] */
+ 0x88, /*= [* ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 77: 'M' */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 78: 'N' */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 79: 'O' */
+ 0x44, /*= [ * ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 80: 'P' */
+ 0xcc, /*= [** ] */
+ 0xaa, /*= [* * ] */
+ 0xcc, /*= [** ] */
+ 0x88, /*= [* ] */
+ 0x88, /*= [* ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 81: 'Q' */
+ 0x44, /*= [ * ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0x66, /*= [ ** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 82: 'R' */
+ 0xcc, /*= [** ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0xcc, /*= [** ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 83: 'S' */
+ 0x66, /*= [ ** ] */
+ 0x88, /*= [* ] */
+ 0x44, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0xcc, /*= [** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 84: 'T' */
+ 0xee, /*= [*** ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 85: 'U' */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x66, /*= [ ** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 86: 'V' */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 87: 'W' */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 88: 'X' */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x44, /*= [ * ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 89: 'Y' */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 90: 'Z' */
+ 0xee, /*= [*** ] */
+ 0x22, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x88, /*= [* ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 91: '[' */
+ 0x66, /*= [ ** ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x66, /*= [ ** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 92: '\' */
+ 0x00, /*= [ ] */
+ 0x88, /*= [* ] */
+ 0x44, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 93: ']' */
+ 0x66, /*= [ ** ] */
+ 0x22, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x66, /*= [ ** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 94: '^' */
+ 0x44, /*= [ * ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 95: '_' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xff, /*= [****] */
+ /*}*/
+ /*{*/ /* Char 96: '`' */
+ 0x88, /*= [* ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 97: 'a' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x66, /*= [ ** ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 98: 'b' */
+ 0x88, /*= [* ] */
+ 0x88, /*= [* ] */
+ 0xcc, /*= [** ] */
+ 0xaa, /*= [* * ] */
+ 0xcc, /*= [** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 99: 'c' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x66, /*= [ ** ] */
+ 0x88, /*= [* ] */
+ 0x66, /*= [ ** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 100: 'd' */
+ 0x22, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x66, /*= [ ** ] */
+ 0xaa, /*= [* * ] */
+ 0x66, /*= [ ** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 101: 'e' */
+ 0x00, /*= [ ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x88, /*= [* ] */
+ 0x66, /*= [ ** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 102: 'f' */
+ 0x22, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0xee, /*= [*** ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 103: 'g' */
+ 0x00, /*= [ ] */
+ 0x66, /*= [ ** ] */
+ 0xaa, /*= [* * ] */
+ 0x66, /*= [ ** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 104: 'h' */
+ 0x88, /*= [* ] */
+ 0x88, /*= [* ] */
+ 0xcc, /*= [** ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 105: 'i' */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 106: 'j' */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x88, /*= [* ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 107: 'k' */
+ 0x00, /*= [ ] */
+ 0x88, /*= [* ] */
+ 0xaa, /*= [* * ] */
+ 0xcc, /*= [** ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 108: 'l' */
+ 0x00, /*= [ ] */
+ 0xcc, /*= [** ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 109: 'm' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 110: 'n' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xcc, /*= [** ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 111: 'o' */
+ 0x00, /*= [ ] */
+ 0x44, /*= [ * ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 112: 'p' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xcc, /*= [** ] */
+ 0xaa, /*= [* * ] */
+ 0xcc, /*= [** ] */
+ 0x88, /*= [* ] */
+ /*}*/
+ /*{*/ /* Char 113: 'q' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x66, /*= [ ** ] */
+ 0xaa, /*= [* * ] */
+ 0x66, /*= [ ** ] */
+ 0x22, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 114: 'r' */
+ 0x00, /*= [ ] */
+ 0xcc, /*= [** ] */
+ 0xaa, /*= [* * ] */
+ 0x88, /*= [* ] */
+ 0x88, /*= [* ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 115: 's' */
+ 0x00, /*= [ ] */
+ 0x66, /*= [ ** ] */
+ 0xcc, /*= [** ] */
+ 0x22, /*= [ * ] */
+ 0xcc, /*= [** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 116: 't' */
+ 0x00, /*= [ ] */
+ 0x44, /*= [ * ] */
+ 0xee, /*= [*** ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 117: 'u' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x66, /*= [ ** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 118: 'v' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 119: 'w' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 120: 'x' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xaa, /*= [* * ] */
+ 0x44, /*= [ * ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 121: 'y' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0x22, /*= [ * ] */
+ 0xcc, /*= [** ] */
+ /*}*/
+ /*{*/ /* Char 122: 'z' */
+ 0x00, /*= [ ] */
+ 0xee, /*= [*** ] */
+ 0x66, /*= [ ** ] */
+ 0xcc, /*= [** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 123: '{' */
+ 0x22, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0xcc, /*= [** ] */
+ 0x44, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 124: '|' */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 125: '}' */
+ 0x88, /*= [* ] */
+ 0x44, /*= [ * ] */
+ 0x66, /*= [ ** ] */
+ 0x44, /*= [ * ] */
+ 0x88, /*= [* ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 126: '~' */
+ 0x55, /*= [ * *] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 127: '' */
+ 0x44, /*= [ * ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 128: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 129: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 130: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 131: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 132: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 133: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 134: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 135: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 136: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 137: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 138: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 139: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 140: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 141: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 142: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 143: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 144: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 145: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 146: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 147: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 148: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 149: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 150: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 151: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 152: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 153: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 154: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 155: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 156: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 157: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 158: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 159: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 160: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 161: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 162: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 163: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 164: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 165: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 166: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 167: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 168: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 169: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 170: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 171: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 172: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 173: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 174: */
+ 0x00, /*= [ ] */
+ 0x66, /*= [ ** ] */
+ 0xcc, /*= [** ] */
+ 0x66, /*= [ ** ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 175: */
+ 0x00, /*= [ ] */
+ 0xcc, /*= [** ] */
+ 0x66, /*= [ ** ] */
+ 0xcc, /*= [** ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 176: */
+ 0x88, /*= [* ] */
+ 0x22, /*= [ * ] */
+ 0x88, /*= [* ] */
+ 0x22, /*= [ * ] */
+ 0x88, /*= [* ] */
+ 0x22, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 177: */
+ 0xaa, /*= [* * ] */
+ 0x55, /*= [ * *] */
+ 0xaa, /*= [* * ] */
+ 0x55, /*= [ * *] */
+ 0xaa, /*= [* * ] */
+ 0x55, /*= [ * *] */
+ /*}*/
+ /*{*/ /* Char 178: */
+ 0xdd, /*= [** *] */
+ 0xbb, /*= [* **] */
+ 0xdd, /*= [** *] */
+ 0xbb, /*= [* **] */
+ 0xdd, /*= [** *] */
+ 0xbb, /*= [* **] */
+ /*}*/
+ /*{*/ /* Char 179: */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 180: */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0xcc, /*= [** ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 181: */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0xcc, /*= [** ] */
+ 0xcc, /*= [** ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 182: */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0xee, /*= [*** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ /*}*/
+ /*{*/ /* Char 183: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xee, /*= [*** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ /*}*/
+ /*{*/ /* Char 184: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xcc, /*= [** ] */
+ 0xcc, /*= [** ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 185: */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ /*}*/
+ /*{*/ /* Char 186: */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ /*}*/
+ /*{*/ /* Char 187: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ /*}*/
+ /*{*/ /* Char 188: */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 189: */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 190: */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0xcc, /*= [** ] */
+ 0xcc, /*= [** ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 191: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xcc, /*= [** ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 192: */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x77, /*= [ ***] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 193: */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0xff, /*= [****] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 194: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xff, /*= [****] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 195: */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x77, /*= [ ***] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 196: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xff, /*= [****] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 197: */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0xff, /*= [****] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 198: */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x77, /*= [ ***] */
+ 0x77, /*= [ ***] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 199: */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x77, /*= [ ***] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ /*}*/
+ /*{*/ /* Char 200: */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x77, /*= [ ***] */
+ 0x77, /*= [ ***] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 201: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x77, /*= [ ***] */
+ 0x77, /*= [ ***] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ /*}*/
+ /*{*/ /* Char 202: */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 203: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ /*}*/
+ /*{*/ /* Char 204: */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x77, /*= [ ***] */
+ 0x77, /*= [ ***] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ /*}*/
+ /*{*/ /* Char 205: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 206: */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ /*}*/
+ /*{*/ /* Char 207: */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 208: */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0xff, /*= [****] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 209: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 210: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xff, /*= [****] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ /*}*/
+ /*{*/ /* Char 211: */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x77, /*= [ ***] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 212: */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x77, /*= [ ***] */
+ 0x77, /*= [ ***] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 213: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x77, /*= [ ***] */
+ 0x77, /*= [ ***] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 214: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x77, /*= [ ***] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ /*}*/
+ /*{*/ /* Char 215: */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0xff, /*= [****] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ /*}*/
+ /*{*/ /* Char 216: */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 217: */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0xcc, /*= [** ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 218: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x77, /*= [ ***] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 219: */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ /*}*/
+ /*{*/ /* Char 220: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ /*}*/
+ /*{*/ /* Char 221: */
+ 0xcc, /*= [** ] */
+ 0xcc, /*= [** ] */
+ 0xcc, /*= [** ] */
+ 0xcc, /*= [** ] */
+ 0xcc, /*= [** ] */
+ 0xcc, /*= [** ] */
+ /*}*/
+ /*{*/ /* Char 222: */
+ 0x33, /*= [ **] */
+ 0x33, /*= [ **] */
+ 0x33, /*= [ **] */
+ 0x33, /*= [ **] */
+ 0x33, /*= [ **] */
+ 0x33, /*= [ **] */
+ /*}*/
+ /*{*/ /* Char 223: */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 224: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 225: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 226: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 227: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 228: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 229: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 230: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 231: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 232: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 233: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 234: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 235: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 236: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 237: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 238: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 239: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 240: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 241: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 242: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 243: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 244: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 245: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 246: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 247: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 248: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 249: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 250: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 251: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 252: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 253: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 254: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 255: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+};
+
+#endif
diff --git a/include/video_font_data.h b/include/video_font_data.h
index 4e544f0..346a162 100644
--- a/include/video_font_data.h
+++ b/include/video_font_data.h
@@ -8,7 +8,12 @@
#ifndef _VIDEO_FONT_DATA_
#define _VIDEO_FONT_DATA_
-static unsigned char video_fontdata[VIDEO_FONT_SIZE] = {
+#define VIDEO_FONT_CHARS 256
+#define VIDEO_FONT_WIDTH 8
+#define VIDEO_FONT_HEIGHT 16
+#define VIDEO_FONT_SIZE (VIDEO_FONT_CHARS * VIDEO_FONT_HEIGHT)
+
+static unsigned char __maybe_unused video_fontdata[VIDEO_FONT_SIZE] = {
/* 0 0x00 '^@' */
0x00, /* 00000000 */
diff --git a/tools/bmp_logo.c b/tools/bmp_logo.c
index b2ad3d5..2247adc 100644
--- a/tools/bmp_logo.c
+++ b/tools/bmp_logo.c
@@ -179,7 +179,7 @@
printf("unsigned char bmp_logo_bitmap[] = {\n");
for (i=(b->height-1)*b->width; i>=0; i-=b->width) {
for (x = 0; x < b->width; x++) {
- b->data[(uint16_t) i + x] = (uint8_t) fgetc (fp) \
+ b->data[i + x] = (uint8_t) fgetc(fp)
+ DEFAULT_CMAP_SIZE;
}
}