blob: d933a9e7c684ec9ae9a185197b90adba39e12ab2 [file] [log] [blame]
/*
* Configuation settings for the SAMA5D3xEK board.
*
* Copyright (C) 2012 - 2013 Atmel
*
* based on at91sam9m10g45ek.h by:
* Stelian Pop <stelian@popies.net>
* Lead Tech Design <www.leadtechdesign.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* If has No NOR flash, please put the definition: CONFIG_SYS_NO_FLASH
* before the common header.
*/
#include "at91-sama5_common.h"
/* serial console */
#define CONFIG_ATMEL_USART
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID ATMEL_ID_DBGU
/*
* This needs to be defined for the OHCI code to work but it is defined as
* ATMEL_ID_UHPHS in the CPU specific header files.
*/
#define ATMEL_ID_UHP ATMEL_ID_UHPHS
/*
* Specify the clock enable bit in the PMC_SCER register.
*/
#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
/* LCD */
#define CONFIG_LCD
#define LCD_BPP LCD_COLOR16
#define LCD_OUTPUT_BPP 24
#define CONFIG_LCD_LOGO
#define CONFIG_LCD_INFO
#define CONFIG_LCD_INFO_BELOW_LOGO
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONFIG_ATMEL_HLCD
#define CONFIG_ATMEL_LCD_RGB565
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
/* board specific (not enough SRAM) */
#define CONFIG_SAMA5D3_LCD_BASE 0x23E00000
/* NOR flash */
#ifndef CONFIG_SYS_NO_FLASH
#define CONFIG_CMD_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_BASE 0x10000000
#define CONFIG_SYS_MAX_FLASH_SECT 131
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#endif
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR 0x310000
#else
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
#endif
/* SerialFlash */
#define CONFIG_CMD_SF
#ifdef CONFIG_CMD_SF
#define CONFIG_ATMEL_SPI
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SF_DEFAULT_SPEED 30000000
#endif
/* NAND flash */
#define CONFIG_CMD_NAND
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ONFI_DETECTION
/* PMECC & PMERRLOC */
#define CONFIG_ATMEL_NAND_HWECC
#define CONFIG_ATMEL_NAND_HW_PMECC
#define CONFIG_PMECC_CAP 4
#define CONFIG_PMECC_SECTOR_SIZE 512
#define CONFIG_CMD_NAND_TRIMFFS
#endif
/* Ethernet Hardware */
#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_MACB_SEARCH_PHY
#define CONFIG_RGMII
#define CONFIG_CMD_MII
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9021
/* MMC */
#define CONFIG_CMD_MMC
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#define ATMEL_BASE_MMCI ATMEL_BASE_MCI0
#endif
/* USB */
#define CONFIG_CMD_USB
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
#define CONFIG_DOS_PARTITION
#define CONFIG_USB_STORAGE
#endif
/* USB device */
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_ATMEL_USBA
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_RNDIS
#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D3xEK"
#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
#define CONFIG_CMD_FAT
#define CONFIG_FAT_WRITE
#endif
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#ifdef CONFIG_SYS_USE_SERIALFLASH
/* bootstrap + u-boot + env + linux in serial flash */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x5000
#define CONFIG_ENV_SIZE 0x3000
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_BOOTCOMMAND "sf probe 0; " \
"sf read 0x22000000 0x42000 0x300000; " \
"bootm 0x22000000"
#elif CONFIG_SYS_USE_NANDFLASH
/* bootstrap + u-boot + env in nandflash */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0xc0000
#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \
"nand read 0x22000000 0x200000 0x600000;" \
"bootm 0x22000000 - 0x21000000"
#elif CONFIG_SYS_USE_MMC
/* bootstrap + u-boot + env in sd card */
#define CONFIG_ENV_IS_IN_FAT
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_FILE "uboot.env"
#define FAT_ENV_DEVICE_AND_PART "0"
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 dtb; " \
"fatload mmc 0:1 0x22000000 uImage; " \
"bootm 0x22000000 - 0x21000000"
#else
#define CONFIG_ENV_IS_NOWHERE
#endif
/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x300000
#define CONFIG_SPL_MAX_SIZE 0x10000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#ifdef CONFIG_SYS_USE_MMC
#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#elif CONFIG_SYS_USE_NANDFLASH
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
#elif CONFIG_SYS_USE_SERIALFLASH
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
#endif
#endif