| /* | |
| * (C) Copyright 2002 | |
| * Rich Ireland, Enterasys Networks, rireland@enterasys.com. | |
| * Keith Outwater, keith_outwater@mvis.com. | |
| * | |
| * SPDX-License-Identifier: GPL-2.0+ | |
| */ | |
| /* | |
| * Virtex2 FPGA configuration support for the QUANTUM computer | |
| */ | |
| int fpga_boot(unsigned char *fpgadata, int size); | |
| #define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */ | |
| #define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */ | |
| #define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */ |