| /* |
| * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> |
| * |
| * SPDX-License-Identifier: GPL-2.0+ |
| */ |
| |
| /dts-v1/; |
| |
| #include <dt-bindings/interrupt-router/intel-irq.h> |
| |
| /include/ "skeleton.dtsi" |
| /include/ "serial.dtsi" |
| /include/ "rtc.dtsi" |
| |
| / { |
| model = "Intel Crown Bay"; |
| compatible = "intel,crownbay", "intel,queensbay"; |
| |
| aliases { |
| spi0 = "/spi"; |
| }; |
| |
| config { |
| silent_console = <0>; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "cpu-x86"; |
| reg = <0>; |
| intel,apic-id = <0>; |
| }; |
| |
| cpu@1 { |
| device_type = "cpu"; |
| compatible = "cpu-x86"; |
| reg = <1>; |
| intel,apic-id = <1>; |
| }; |
| |
| }; |
| |
| gpioa { |
| compatible = "intel,ich6-gpio"; |
| u-boot,dm-pre-reloc; |
| reg = <0 0x20>; |
| bank-name = "A"; |
| }; |
| |
| gpiob { |
| compatible = "intel,ich6-gpio"; |
| u-boot,dm-pre-reloc; |
| reg = <0x20 0x20>; |
| bank-name = "B"; |
| }; |
| |
| chosen { |
| /* |
| * By default the legacy superio serial port is used as the |
| * U-Boot serial console. If we want to use UART from Topcliff |
| * PCH as the console, change this property to &pciuart#. |
| * |
| * For example, stdout-path = &pciuart0 will use the first |
| * UART on Topcliff PCH. |
| */ |
| stdout-path = "/serial"; |
| }; |
| |
| spi { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "intel,ich-spi"; |
| spi-flash@0 { |
| reg = <0>; |
| compatible = "sst,25vf016b", "spi-flash"; |
| memory-map = <0xffe00000 0x00200000>; |
| }; |
| }; |
| |
| microcode { |
| update@0 { |
| #include "microcode/m0220661105_cv.dtsi" |
| }; |
| }; |
| |
| pci { |
| #address-cells = <3>; |
| #size-cells = <2>; |
| compatible = "pci-x86"; |
| u-boot,dm-pre-reloc; |
| ranges = <0x02000000 0x0 0x40000000 0x40000000 0 0x80000000 |
| 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 |
| 0x01000000 0x0 0x2000 0x2000 0 0xe000>; |
| |
| pcie@17,0 { |
| #address-cells = <3>; |
| #size-cells = <2>; |
| compatible = "pci-bridge"; |
| u-boot,dm-pre-reloc; |
| reg = <0x0000b800 0x0 0x0 0x0 0x0>; |
| |
| topcliff@0,0 { |
| #address-cells = <3>; |
| #size-cells = <2>; |
| compatible = "pci-bridge"; |
| u-boot,dm-pre-reloc; |
| reg = <0x00010000 0x0 0x0 0x0 0x0>; |
| |
| pciuart0: uart@a,1 { |
| compatible = "pci8086,8811.00", |
| "pci8086,8811", |
| "pciclass,070002", |
| "pciclass,0700", |
| "x86-uart"; |
| u-boot,dm-pre-reloc; |
| reg = <0x00025100 0x0 0x0 0x0 0x0 |
| 0x01025110 0x0 0x0 0x0 0x0>; |
| reg-shift = <0>; |
| clock-frequency = <1843200>; |
| current-speed = <115200>; |
| }; |
| |
| pciuart1: uart@a,2 { |
| compatible = "pci8086,8812.00", |
| "pci8086,8812", |
| "pciclass,070002", |
| "pciclass,0700", |
| "x86-uart"; |
| u-boot,dm-pre-reloc; |
| reg = <0x00025200 0x0 0x0 0x0 0x0 |
| 0x01025210 0x0 0x0 0x0 0x0>; |
| reg-shift = <0>; |
| clock-frequency = <1843200>; |
| current-speed = <115200>; |
| }; |
| |
| pciuart2: uart@a,3 { |
| compatible = "pci8086,8813.00", |
| "pci8086,8813", |
| "pciclass,070002", |
| "pciclass,0700", |
| "x86-uart"; |
| u-boot,dm-pre-reloc; |
| reg = <0x00025300 0x0 0x0 0x0 0x0 |
| 0x01025310 0x0 0x0 0x0 0x0>; |
| reg-shift = <0>; |
| clock-frequency = <1843200>; |
| current-speed = <115200>; |
| }; |
| |
| pciuart3: uart@a,4 { |
| compatible = "pci8086,8814.00", |
| "pci8086,8814", |
| "pciclass,070002", |
| "pciclass,0700", |
| "x86-uart"; |
| u-boot,dm-pre-reloc; |
| reg = <0x00025400 0x0 0x0 0x0 0x0 |
| 0x01025410 0x0 0x0 0x0 0x0>; |
| reg-shift = <0>; |
| clock-frequency = <1843200>; |
| current-speed = <115200>; |
| }; |
| }; |
| }; |
| |
| irq-router@1f,0 { |
| reg = <0x0000f800 0 0 0 0>; |
| compatible = "intel,irq-router"; |
| intel,pirq-config = "pci"; |
| intel,pirq-link = <0x60 8>; |
| intel,pirq-mask = <0xcee0>; |
| intel,pirq-routing = < |
| /* TunnelCreek PCI devices */ |
| PCI_BDF(0, 2, 0) INTA PIRQE |
| PCI_BDF(0, 3, 0) INTA PIRQF |
| PCI_BDF(0, 23, 0) INTA PIRQA |
| PCI_BDF(0, 23, 0) INTB PIRQB |
| PCI_BDF(0, 23, 0) INTC PIRQC |
| PCI_BDF(0, 23, 0) INTD PIRQD |
| PCI_BDF(0, 24, 0) INTA PIRQB |
| PCI_BDF(0, 24, 0) INTB PIRQC |
| PCI_BDF(0, 24, 0) INTC PIRQD |
| PCI_BDF(0, 24, 0) INTD PIRQA |
| PCI_BDF(0, 25, 0) INTA PIRQC |
| PCI_BDF(0, 25, 0) INTB PIRQD |
| PCI_BDF(0, 25, 0) INTC PIRQA |
| PCI_BDF(0, 25, 0) INTD PIRQB |
| PCI_BDF(0, 26, 0) INTA PIRQD |
| PCI_BDF(0, 26, 0) INTB PIRQA |
| PCI_BDF(0, 26, 0) INTC PIRQB |
| PCI_BDF(0, 26, 0) INTD PIRQC |
| PCI_BDF(0, 27, 0) INTA PIRQG |
| /* |
| * Topcliff PCI devices |
| * |
| * Note on the Crown Bay board, Topcliff chipset |
| * is connected to TunnelCreek PCIe port 0, so |
| * its bus number is 1 for its PCIe port and 2 |
| * for its PCI devices per U-Boot current PCI |
| * bus enumeration algorithm. |
| */ |
| PCI_BDF(1, 0, 0) INTA PIRQA |
| PCI_BDF(2, 0, 1) INTA PIRQA |
| PCI_BDF(2, 0, 2) INTA PIRQA |
| PCI_BDF(2, 2, 0) INTB PIRQD |
| PCI_BDF(2, 2, 1) INTB PIRQD |
| PCI_BDF(2, 2, 2) INTB PIRQD |
| PCI_BDF(2, 2, 3) INTB PIRQD |
| PCI_BDF(2, 2, 4) INTB PIRQD |
| PCI_BDF(2, 4, 0) INTC PIRQC |
| PCI_BDF(2, 4, 1) INTC PIRQC |
| PCI_BDF(2, 6, 0) INTD PIRQB |
| PCI_BDF(2, 8, 0) INTA PIRQA |
| PCI_BDF(2, 8, 1) INTA PIRQA |
| PCI_BDF(2, 8, 2) INTA PIRQA |
| PCI_BDF(2, 8, 3) INTA PIRQA |
| PCI_BDF(2, 10, 0) INTB PIRQD |
| PCI_BDF(2, 10, 1) INTB PIRQD |
| PCI_BDF(2, 10, 2) INTB PIRQD |
| PCI_BDF(2, 10, 3) INTB PIRQD |
| PCI_BDF(2, 10, 4) INTB PIRQD |
| PCI_BDF(2, 12, 0) INTC PIRQC |
| PCI_BDF(2, 12, 1) INTC PIRQC |
| PCI_BDF(2, 12, 2) INTC PIRQC |
| PCI_BDF(2, 12, 3) INTC PIRQC |
| PCI_BDF(2, 12, 4) INTC PIRQC |
| >; |
| }; |
| }; |
| |
| }; |