| ----------------------------- |
| NAND boot on PPC440 platforms |
| ----------------------------- |
| |
| This document describes the U-Boot NAND boot feature as it |
| is implemented for the AMCC Sequoia (PPC440EPx) board. |
| |
| The PPC440EP(x)/GR(x) cpu's can boot directly from NAND FLASH, |
| completely without NOR FLASH. This can be done by using the NAND |
| boot feature of the 440 NAND flash controller (NDFC). |
| |
| Here a short desciption of the different boot stages: |
| |
| a) IPL (Initial Program Loader, integrated inside CPU) |
| ------------------------------------------------------ |
| Will load first 4k from NAND (SPL) into cache and execute it from there. |
| |
| b) SPL (Secondary Program Loader) |
| --------------------------------- |
| Will load special U-Boot version (NUB) from NAND and execute it. This SPL |
| has to fit into 4kByte. It sets up the CPU and configures the SDRAM |
| controller and the NAND controller so that the special U-Boot image can be |
| loaded from NAND to SDRAM. |
| This special image is build in the directory "nand_spl". |
| |
| c) NUB (NAND U-Boot) |
| -------------------- |
| This NAND U-Boot (NUB) is a special U-Boot version which can be started |
| from RAM. Therefore it mustn't (re-)configure the SDRAM controller. |
| |
| On 440EPx the SPL is copied to internal SRAM before the NAND controller |
| is set up. While still running from cache, I experienced problems accessing |
| the NAND controller. |
| |
| |
| September 07 2006, Stefan Roese <sr@denx.de> |