board/freescale/mpc8641hpcn/README

Freescale MPC8641HPCN board
===========================

Created 05/24/2006 Haiying Wang
-------------------------------

1. Building U-Boot
------------------
The 86xx HPCN code base is known to compile using:
    Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3

    $ make MPC8641HPCN_config
    Configuring for MPC8641HPCN board...

    $ make


2. Switch and Jumper Setting
----------------------------
Jumpers:
	J14 Pins 1-2 (near plcc32 socket)

Switches:
	SW1(1-5) = 01100	CONFIG_SYS_COREPLL	= 01000 :: CORE =   2:1
						  01100 :: CORE = 2.5:1
						  10000 :: CORE =   3:1
						  11100 :: CORE = 3.5:1
						  10100 :: CORE =   4:1
						  01110 :: CORE = 4.5:1
	SW1(6-8) = 001		CONFIG_SYS_SYSCLK	= 000	:: SYSCLK = 33MHz
						  001	:: SYSCLK = 40MHz

	SW2(1-4) = 1100		CONFIG_SYS_CCBPLL	= 0010	:: 2X
						  0100	:: 4X
						  0110	:: 6X
						  1000	:: 8X
						  1010	:: 10X
						  1100	:: 12X
						  1110	:: 14X
						  0000	:: 16X
	SW2(5-8) = 1110		CONFIG_SYS_BOOTLOC	= 1110	:: boot 16-bit localbus

	SW3(1-7) = 0011000	CONFIG_SYS_VID		= 0011000 :: VCORE = 1.2V
						  0100000 :: VCORE = 1.11V
	SW3(8)	 = 0		VCC_PLAT	= 0	:: VCC_PLAT = 1.2V
						  1	:: VCC_PLAT = 1.0V

	SW4(1-2) = 11		CONFIG_SYS_HOSTMODE	= 11	:: both prots host/root
	SW4(3-4) = 11		CONFIG_SYS_BOOTSEQ	= 11	:: no boot seq
	SW4(5-8) = 0011		CONFIG_SYS_IOPORT	= 0011	:: both PEX

	SW5(1)	 = 1		CONFIG_SYS_FLASHMAP	= 1	:: boot from flash
						  0	:: boot from PromJet
	SW5(2)	 = 1		CONFIG_SYS_FLASHBANK	= 1	:: swap upper/lower
							 halves (virtual banks)
						  0	:: normal
	SW5(3)	 = 0		CONFIG_SYS_FLASHWP	= 0	:: not protected
	SW5(4)	 = 0		CONFIG_SYS_PORTDIV	= 1	:: 2:1 for PD4
							   1:1 for PD6
	SW5(5-6) = 11		CONFIG_SYS_PIXISOPT	= 11	:: s/w determined
	SW5(7-8) = 11		CONFIG_SYS_LADOPT	= 11	:: s/w determined

	SW6(1)	 = 1		CONFIG_SYS_CPUBOOT	= 1	:: no boot holdoff
	SW6(2)	 = 1		CONFIG_SYS_BOOTADDR	= 1	:: no traslation
	SW6(3-5) = 000		CONFIG_SYS_REFCLKSEL	= 000	:: 100MHZ
	SW6(6)	 = 1		CONFIG_SYS_SERROM_ADDR= 1	::
	SW6(7)	 = 1		CONFIG_SYS_MEMDEBUG	= 1	::
	SW6(8)	 = 1		CONFIG_SYS_DDRDEBUG	= 1	::

	SW8(1)	 = 1		ACZ_SYNC	= 1	:: 48MHz on TP49
	SW8(2)	 = 1		ACB_SYNC	= 1	:: THRMTRIP disabled
	SW8(3)	 = 1		ACZ_SDOUT	= 1	:: p4 mode
	SW8(4)	 = 1		ACB_SDOUT	= 1	:: PATA freq. = 133MHz
	SW8(5)	 = 0		SUSLED		= 0	:: SouthBridge Mode
	SW8(6)	 = 0		SPREAD		= 0	:: REFCLK SSCG Disabled
	SW8(7)	 = 1		ACPWR		= 1	:: non-battery
	SW8(8)	 = 0		CONFIG_SYS_IDWP	= 0	:: write enable


3. Flash U-Boot
---------------
The flash range 0xEF800000 to 0xEFFFFFFF can be divided into 2 halves.
It is possible to use either half to boot using u-boot.  Switch 5 bit 2
is used for this purpose.

0xEF800000 to 0xEFBFFFFF - 4MB
0xEFC00000 to 0xEFFFFFFF - 4MB
When this bit is 0, U-Boot is at 0xEFF00000.
When this bit is 1, U-Boot is at 0xEFB00000.

Use the above mentioned flash commands to program the other half, and
use switch 5, bit 2 to alternate between the halves.  Note: The booting
version of U-Boot will always be at 0xEFF00000.

To Flash U-Boot into the booting bank (0xEFC00000 - 0xEFFFFFFF):

	tftp 1000000 u-boot.bin
	protect off all
	erase eff00000 +$filesize
	cp.b 1000000 eff00000 $filesize

or use tftpflash command:
	run tftpflash

To Flash U-boot into the alternative bank (0xEF800000 - 0xEFBFFFFF):

	tftp 1000000 u-boot.bin
	erase efb00000 +$filesize
	cp.b 1000000 efb00000 $filesize


4. Memory Map
-------------
NOTE:  RIO and PCI are mutually exclusive, so they share an address

For 32-bit u-boot, devices are mapped so that the virtual address ==
the physical address, and the map looks liks this:

	Memory Range			Device		Size
	------------			------		----
	0x0000_0000	0x7fff_ffff	DDR		2G
	0x8000_0000	0x9fff_ffff	RIO MEM		512M
	0x8000_0000	0x9fff_ffff	PCI1/PEX1 MEM	512M
	0xa000_0000	0xbfff_ffff	PCI2/PEX2 MEM	512M
	0xffe0_0000	0xffef_ffff	CCSR		1M
	0xffdf_0000	0xffdf_7fff	PIXIS		8K
	0xffdf_8000	0xffdf_ffff	CF		8K
	0xf840_0000	0xf840_3fff	Stack space	32K
	0xffc0_0000	0xffc0_ffff	PCI1/PEX1 IO	64K
	0xffc1_0000	0xffc1_ffff	PCI2/PEX2 IO	64K
	0xef80_0000	0xefff_ffff	Flash		8M

For 36-bit-enabled u-boot, the virtual map is the same as for 32-bit.
However, the physical map is altered to reside in 36-bit space, as follows.
Addresses are no longer mapped with VA == PA.  All accesses from
software use the VA; the PA is only used for setting up windows
and mappings. Note that with the exception of PCI MEM and RIO, the low
 32 bits are the same as the VA above; only the top 4 bits vary:

	Memory Range			Device		Size
	------------			------		----
	0x0_0000_0000	0x0_7fff_ffff	DDR		2G
	0xc_0000_0000	0xc_1fff_ffff	RIO MEM		512M
	0xc_0000_0000	0xc_1fff_ffff	PCI1/PEX1 MEM	512M
	0xc_2000_0000	0xc_3fff_ffff	PCI2/PEX2 MEM	512M
	0xf_ffe0_0000	0xf_ffef_ffff	CCSR		1M
	0xf_ffdf_0000	0xf_ffdf_7fff	PIXIS		8K
	0xf_ffdf_8000	0xf_ffdf_ffff	CF		8K
	0x0_f840_0000	0xf_f840_3fff	Stack space	32K
	0xf_ffc0_0000	0xf_ffc0_ffff	PCI1/PEX1 IO	64K
	0xf_ffc1_0000	0xf_ffc1_ffff	PCI2/PEX2 IO	64K
	0xf_ef80_0000	0xf_efff_ffff	Flash		8M

5. pixis_reset command
--------------------
A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
using the FPGA sequencer.  When the board restarts, it has the option
of using either the current or alternate flash bank as the boot
image, with or without the watchdog timer enabled, and finally with
or without frequency changes.

Usage is;

	pixis_reset
	pixis_reset altbank
	pixis_reset altbank wd
	pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
	pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>

Examples;

	/* reset to current bank, like "reset" command */
	pixis_reset

	/* reset board but use the to alternate flash bank */
	pixis_reset altbank

	/* reset board, use alternate flash bank with watchdog timer enabled*/
	pixis_reset altbank wd

	/* reset board to alternate bank with frequency changed.
	 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
	 */
	pixis-reset altbank cf 40 2.5 10

Valid clock choices are in the 8641 Reference Manuals.