| /* |
| * Copyright 2014-2015 Freescale Semiconductor |
| * |
| * SPDX-License-Identifier: GPL-2.0+ |
| */ |
| |
| #include <common.h> |
| #include <fsl_ifc.h> |
| #include <asm/arch/soc.h> |
| #include <asm/io.h> |
| #include <asm/global_data.h> |
| #include <asm/arch-fsl-layerscape/config.h> |
| |
| DECLARE_GLOBAL_DATA_PTR; |
| |
| #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) |
| #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 |
| #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val" |
| |
| static unsigned long get_internval_val_mhz(void) |
| { |
| char *interval = getenv(PLATFORM_CYCLE_ENV_VAR); |
| /* |
| * interval is the number of platform cycles(MHz) between |
| * wake up events generated by EPU. |
| */ |
| ulong interval_mhz = get_bus_freq(0) / (1000 * 1000); |
| |
| if (interval) |
| interval_mhz = simple_strtoul(interval, NULL, 10); |
| |
| return interval_mhz; |
| } |
| |
| void erratum_a009635(void) |
| { |
| u32 val; |
| unsigned long interval_mhz = get_internval_val_mhz(); |
| |
| if (!interval_mhz) |
| return; |
| |
| val = in_le32(DCSR_CGACRE5); |
| writel(val | 0x00000200, DCSR_CGACRE5); |
| |
| val = in_le32(EPU_EPCMPR5); |
| writel(interval_mhz, EPU_EPCMPR5); |
| val = in_le32(EPU_EPCCR5); |
| writel(val | 0x82820000, EPU_EPCCR5); |
| val = in_le32(EPU_EPSMCR5); |
| writel(val | 0x002f0000, EPU_EPSMCR5); |
| val = in_le32(EPU_EPECR5); |
| writel(val | 0x20000000, EPU_EPECR5); |
| val = in_le32(EPU_EPGCR); |
| writel(val | 0x80000000, EPU_EPGCR); |
| } |
| #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */ |
| |
| static void erratum_a008751(void) |
| { |
| #ifdef CONFIG_SYS_FSL_ERRATUM_A008751 |
| u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; |
| |
| writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4); |
| #endif |
| } |
| |
| static void erratum_rcw_src(void) |
| { |
| #if defined(CONFIG_SPL) |
| u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; |
| u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE; |
| u32 val; |
| |
| val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); |
| val &= ~DCFG_PORSR1_RCW_SRC; |
| val |= DCFG_PORSR1_RCW_SRC_NOR; |
| out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val); |
| #endif |
| } |
| |
| #define I2C_DEBUG_REG 0x6 |
| #define I2C_GLITCH_EN 0x8 |
| /* |
| * This erratum requires setting glitch_en bit to enable |
| * digital glitch filter to improve clock stability. |
| */ |
| static void erratum_a009203(void) |
| { |
| u8 __iomem *ptr; |
| #ifdef CONFIG_SYS_I2C |
| #ifdef I2C1_BASE_ADDR |
| ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG); |
| |
| writeb(I2C_GLITCH_EN, ptr); |
| #endif |
| #ifdef I2C2_BASE_ADDR |
| ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG); |
| |
| writeb(I2C_GLITCH_EN, ptr); |
| #endif |
| #ifdef I2C3_BASE_ADDR |
| ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG); |
| |
| writeb(I2C_GLITCH_EN, ptr); |
| #endif |
| #ifdef I2C4_BASE_ADDR |
| ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG); |
| |
| writeb(I2C_GLITCH_EN, ptr); |
| #endif |
| #endif |
| } |
| |
| void fsl_lsch3_early_init_f(void) |
| { |
| erratum_a008751(); |
| erratum_rcw_src(); |
| init_early_memctl_regs(); /* tighten IFC timing */ |
| erratum_a009203(); |
| } |
| |
| #elif defined(CONFIG_LS1043A) |
| void fsl_lsch2_early_init_f(void) |
| { |
| struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; |
| |
| #ifdef CONFIG_FSL_IFC |
| init_early_memctl_regs(); /* tighten IFC timing */ |
| #endif |
| |
| /* |
| * Enable snoop requests and DVM message requests for |
| * Slave insterface S4 (A53 core cluster) |
| */ |
| out_le32(&cci->slave[4].snoop_ctrl, |
| CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); |
| } |
| #endif |
| |
| #ifdef CONFIG_BOARD_LATE_INIT |
| int board_late_init(void) |
| { |
| return 0; |
| } |
| #endif |