| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright (C) 2022 Philippe Reynes <philippe.reynes@softathome.com> |
| * Copyright 2022 Broadcom Ltd. |
| */ |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| |
| / { |
| compatible = "brcm,bcm6855", "brcm,bcmbca"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| interrupt-parent = <&gic>; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| CA7_0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a7"; |
| reg = <0x0>; |
| next-level-cache = <&L2_0>; |
| enable-method = "psci"; |
| }; |
| |
| CA7_1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a7"; |
| reg = <0x1>; |
| next-level-cache = <&L2_0>; |
| enable-method = "psci"; |
| }; |
| |
| CA7_2: cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a7"; |
| reg = <0x2>; |
| next-level-cache = <&L2_0>; |
| enable-method = "psci"; |
| }; |
| |
| L2_0: l2-cache0 { |
| compatible = "cache"; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv7-timer"; |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>; |
| arm,cpu-registers-not-fw-configured; |
| }; |
| |
| pmu: pmu { |
| compatible = "arm,cortex-a7-pmu"; |
| interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>; |
| }; |
| |
| clocks: clocks { |
| bootph-all; |
| |
| periph_clk: periph-clk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <200000000>; |
| }; |
| |
| uart_clk: uart-clk { |
| compatible = "fixed-factor-clock"; |
| #clock-cells = <0>; |
| clocks = <&periph_clk>; |
| clock-div = <4>; |
| clock-mult = <1>; |
| }; |
| |
| hsspi_pll: hsspi-pll { |
| compatible = "fixed-factor-clock"; |
| #clock-cells = <0>; |
| clocks = <&periph_clk>; |
| clock-mult = <2>; |
| clock-div = <1>; |
| }; |
| |
| wdt_clk: wdt-clk { |
| compatible = "fixed-factor-clock"; |
| #clock-cells = <0>; |
| clocks = <&periph_clk>; |
| clock-div = <4>; |
| clock-mult = <1>; |
| }; |
| }; |
| |
| psci { |
| compatible = "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| axi@81000000 { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0x81000000 0x8000>; |
| |
| gic: interrupt-controller@1000 { |
| compatible = "arm,cortex-a7-gic"; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>; |
| reg = <0x1000 0x1000>, |
| <0x2000 0x2000>, |
| <0x4000 0x2000>, |
| <0x6000 0x2000>; |
| }; |
| }; |
| |
| bus@ff800000 { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0xff800000 0x800000>; |
| bootph-all; |
| |
| uart0: serial@12000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0x12000 0x1000>; |
| interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&uart_clk>, <&uart_clk>; |
| clock-names = "uartclk", "apb_pclk"; |
| status = "disabled"; |
| }; |
| |
| wdt1: watchdog@480 { |
| compatible = "brcm,bcm6345-wdt"; |
| reg = <0x480 0x14>; |
| clocks = <&wdt_clk>; |
| }; |
| |
| wdt2: watchdog@4c0 { |
| compatible = "brcm,bcm6345-wdt"; |
| reg = <0x4c0 0x14>; |
| clocks = <&wdt_clk>; |
| }; |
| |
| wdt-reboot { |
| compatible = "wdt-reboot"; |
| wdt = <&wdt1>; |
| }; |
| |
| gpio0: gpio-controller@500 { |
| compatible = "brcm,bcm6345-gpio"; |
| reg = <0x500 0x4>, |
| <0x520 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| status = "disabled"; |
| }; |
| |
| gpio1: gpio-controller@504 { |
| compatible = "brcm,bcm6345-gpio"; |
| reg = <0x504 0x4>, |
| <0x524 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| status = "disabled"; |
| }; |
| |
| gpio2: gpio-controller@508 { |
| compatible = "brcm,bcm6345-gpio"; |
| reg = <0x508 0x4>, |
| <0x528 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| status = "disabled"; |
| }; |
| |
| gpio3: gpio-controller@50c { |
| compatible = "brcm,bcm6345-gpio"; |
| reg = <0x50c 0x4>, |
| <0x52c 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| status = "disabled"; |
| }; |
| |
| gpio4: gpio-controller@510 { |
| compatible = "brcm,bcm6345-gpio"; |
| reg = <0x510 0x4>, |
| <0x530 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| status = "disabled"; |
| }; |
| |
| gpio5: gpio-controller@514 { |
| compatible = "brcm,bcm6345-gpio"; |
| reg = <0x514 0x4>, |
| <0x534 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| status = "disabled"; |
| }; |
| |
| gpio6: gpio-controller@518 { |
| compatible = "brcm,bcm6345-gpio"; |
| reg = <0x518 0x4>, |
| <0x538 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| status = "disabled"; |
| }; |
| |
| gpio7: gpio-controller@51c { |
| compatible = "brcm,bcm6345-gpio"; |
| reg = <0x51c 0x4>, |
| <0x53c 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| status = "disabled"; |
| }; |
| |
| nand: nand-controller@1800 { |
| compatible = "brcm,nand-bcm6753", |
| "brcm,brcmnand-v5.0", |
| "brcm,brcmnand"; |
| reg-names = "nand", "nand-int-base", "nand-cache"; |
| reg = <0x1800 0x180>, |
| <0x2000 0x10>, |
| <0x1c00 0x200>; |
| parameter-page-big-endian = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| leds: led-controller@3000 { |
| compatible = "brcm,bcm6753-leds"; |
| reg = <0x3000 0x3480>; |
| |
| status = "disabled"; |
| }; |
| }; |
| }; |