blob: e56062a1d03287ca7da0388af819606f5fb58e37 [file] [log] [blame]
menu "i.MX8ULP DDR controllers"
depends on ARCH_IMX8ULP
config IMX8ULP_DRAM
bool "imx8m dram"
config IMX8ULP_DRAM_PHY_PLL_BYPASS
bool "Enable the DDR PHY PLL bypass mode, so PHY clock is from DDR_CLK "
depends on IMX8ULP_DRAM
endmenu