include/configs/canmb.h - github/trini/u-boot - Gitiles

 /*
  * (C) Copyright 2005
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */

 #ifndef __CONFIG_H
 #define __CONFIG_H

 /*
  * High Level Configuration Options
  * (easy to change)
  */

 #define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
 #define CONFIG_MPC5200		1	/* More exactly a MPC5200 */
 #define CONFIG_CANMB  		1	/* ... on canmb board - we need this for FEC.C */

 #define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */

 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */

 #define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif

 #define CONFIG_BOARD_EARLY_INIT_R

 /*
  * Serial console configuration
  */
 #define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
 #define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

 /*
  * Supported commands
  */
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_ASKENV	| \
 				CFG_CMD_DATE	| \
 				CFG_CMD_DHCP	| \
 				CFG_CMD_IMMAP	| \
 				CFG_CMD_MII 	| \
 				CFG_CMD_NFS	| \
 				CFG_CMD_REGINFO	| \
 				CFG_CMD_SNTP	)

 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>

 /*
  * MUST be low boot - HIGHBOOT is not supported anymore
  */
 #if (TEXT_BASE == 0xFE000000)		/* Boot low with 32 MB Flash */
 #   define CFG_LOWBOOT		1
 #   define CFG_LOWBOOT16	1
 #else
 #   error "TEXT_BASE must be 0xFE000000"
 #endif

 /*
  * Autobooting
  */
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 	"echo"

 #undef	CONFIG_BOOTARGS

 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=$(serverip):$(rootpath)\0"			\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
 	"addip=setenv bootargs $(bootargs) "				\
 		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
 		":$(hostname):$(netdev):off panic=1\0"			\
 	"flash_nfs=run nfsargs addip;"					\
 		"bootm $(kernel_addr)\0"				\
 	"flash_self=run ramargs addip;"					\
 		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
 	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
 	"rootpath=/opt/eldk/ppc_6xx\0"					\
 	"bootfile=/tftpboot/canmb/uImage\0"				\
 	""

 #define CONFIG_BOOTCOMMAND	"run flash_self"

 /*
  * IPB Bus clocking configuration.
  */
 #undef CFG_IPBSPEED_133   		/* define for 133MHz speed */

 /*
  * Flash configuration, expect one 16 Megabyte Bank at most
  */
 #define CFG_FLASH_BASE		0xFE000000
 #define CFG_FLASH_SIZE		0x02000000
 #define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
 #define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */

 #define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
 #define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */

 #define CFG_FLASH_CFI_DRIVER
 #define CFG_FLASH_CFI
 #define CFG_FLASH_EMPTY_INFO

 /*
  * DRAM configuration
  */
 #define	CFG_DRAM_DDR		0
 #define CFG_DRAM_EMODE		0
 #define CFG_DRAM_MODE		0x00CD
 #define CFG_DRAM_CONTROL	0x514F0000
 #define CFG_DRAM_CONFIG1	0xD2333A00
 #define CFG_DRAM_CONFIG2	0x8AD70004
 #define	CFG_DRAM_TAP_DEL	0x08
 #define CFG_DRAM_RAM_SIZE	0x19

 /*
  * Environment settings
  */
 #define CFG_ENV_IS_IN_FLASH	1
 #define CFG_ENV_OFFSET		(2*128*1024)
 #define CFG_ENV_SIZE		0x2000
 #define CFG_ENV_SECT_SIZE       (128*1024)

 /*
  * Memory map
  *
  * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
  */
 #define CFG_MBAR			0xf0000000	/* DO NOT CHANGE this */
 #define CFG_SDRAM_BASE		0x00000000
 #define CFG_DEFAULT_MBAR	0x80000000

 /* Use SRAM until RAM will be available */
 #define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
 #define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */


 #define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

 #define CFG_MONITOR_BASE    TEXT_BASE
 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 #   define CFG_RAMBOOT		1
 #endif

 #define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 #define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

 /*
  * Ethernet configuration
  */
 #define CONFIG_MPC5xxx_FEC	1
 #define	CONFIG_PHY_ADDR		0x1
 /*
  * GPIO configuration:
  * PSC1,2,3 predefined as UART
  * PCI disabled
  * Ethernet 100 with MD
  */
 #define CFG_GPS_PORT_CONFIG	0x00058444

 /*
  * Miscellaneous configurable options
  */
 #define CFG_LONGHELP			/* undef to save memory	    */
 #define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #  define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
 #  define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
 #define CFG_MAXARGS		16		/* max number of command args	*/
 #define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

 #define CFG_MEMTEST_START	0x00100000	/* memtest works on */
 #define CFG_MEMTEST_END		0x01f00000	/* 1 ... 31 MB in DRAM	*/

 #define CFG_LOAD_ADDR		0x200000	/* default load address */

 #define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

 #define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */

 /*
  * Various low-level settings
  */
 #define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CFG_HID0_FINAL		HID0_ICE

 #define CFG_BOOTCS_START	CFG_FLASH_BASE
 #define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
 #define CFG_BOOTCS_CFG		0x00047D01
 #define CFG_CS0_START		CFG_FLASH_BASE
 #define CFG_CS0_SIZE		CFG_FLASH_SIZE

 #define CFG_CS_BURST		0x00000000
 #define CFG_CS_DEADCYCLE	0x33333333

 #define CFG_RESET_ADDRESS	0x7f000000

 #endif /* __CONFIG_H */
	/*
	* (C) Copyright 2005
	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	*
	* See file CREDITS for list of people who contributed to this
	* project.
	*
	* This program is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of
	* the License, or (at your option) any later version.
	*
	* This program is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* You should have received a copy of the GNU General Public License
	* along with this program; if not, write to the Free Software
	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	* MA 02111-1307 USA
	*/

	#ifndef __CONFIG_H
	#define __CONFIG_H

	/*
	* High Level Configuration Options
	* (easy to change)
	*/

	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
	#define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */

	#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */

	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	#define BOOTFLAG_WARM 0x02 /* Software reboot */

	#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	#endif

	#define CONFIG_BOARD_EARLY_INIT_R

	/*
	* Serial console configuration
	*/
	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }

	/*
	* Supported commands
	*/
	#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \| \
	CFG_CMD_ASKENV \| \
	CFG_CMD_DATE \| \
	CFG_CMD_DHCP \| \
	CFG_CMD_IMMAP \| \
	CFG_CMD_MII \| \
	CFG_CMD_NFS \| \
	CFG_CMD_REGINFO \| \
	CFG_CMD_SNTP )

	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	#include <cmd_confdefs.h>

	/*
	* MUST be low boot - HIGHBOOT is not supported anymore
	*/
	#if (TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */
	# define CFG_LOWBOOT 1
	# define CFG_LOWBOOT16 1
	#else
	# error "TEXT_BASE must be 0xFE000000"
	#endif

	/*
	* Autobooting
	*/
	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */

	#define CONFIG_PREBOOT "echo;" \
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

	#undef CONFIG_BOOTARGS

	#define CONFIG_EXTRA_ENV_SETTINGS \
	"netdev=eth0\0" \
	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	"nfsroot=$(serverip):$(rootpath)\0" \
	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	"addip=setenv bootargs $(bootargs) " \
	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
	":$(hostname):$(netdev):off panic=1\0" \
	"flash_nfs=run nfsargs addip;" \
	"bootm $(kernel_addr)\0" \
	"flash_self=run ramargs addip;" \
	"bootm $(kernel_addr) $(ramdisk_addr)\0" \
	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
	"rootpath=/opt/eldk/ppc_6xx\0" \
	"bootfile=/tftpboot/canmb/uImage\0" \
	""

	#define CONFIG_BOOTCOMMAND "run flash_self"

	/*
	* IPB Bus clocking configuration.
	*/
	#undef CFG_IPBSPEED_133 /* define for 133MHz speed */

	/*
	* Flash configuration, expect one 16 Megabyte Bank at most
	*/
	#define CFG_FLASH_BASE 0xFE000000
	#define CFG_FLASH_SIZE 0x02000000
	#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
	#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */

	#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */

	#define CFG_FLASH_CFI_DRIVER
	#define CFG_FLASH_CFI
	#define CFG_FLASH_EMPTY_INFO

	/*
	* DRAM configuration
	*/
	#define CFG_DRAM_DDR 0
	#define CFG_DRAM_EMODE 0
	#define CFG_DRAM_MODE 0x00CD
	#define CFG_DRAM_CONTROL 0x514F0000
	#define CFG_DRAM_CONFIG1 0xD2333A00
	#define CFG_DRAM_CONFIG2 0x8AD70004
	#define CFG_DRAM_TAP_DEL 0x08
	#define CFG_DRAM_RAM_SIZE 0x19

	/*
	* Environment settings
	*/
	#define CFG_ENV_IS_IN_FLASH 1
	#define CFG_ENV_OFFSET (21281024)
	#define CFG_ENV_SIZE 0x2000
	#define CFG_ENV_SECT_SIZE (128*1024)

	/*
	* Memory map
	*
	* Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
	*/
	#define CFG_MBAR 0xf0000000 /* DO NOT CHANGE this */
	#define CFG_SDRAM_BASE 0x00000000
	#define CFG_DEFAULT_MBAR 0x80000000

	/* Use SRAM until RAM will be available */
	#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
	#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */


	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET

	#define CFG_MONITOR_BASE TEXT_BASE
	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	# define CFG_RAMBOOT 1
	#endif

	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */

	/*
	* Ethernet configuration
	*/
	#define CONFIG_MPC5xxx_FEC 1
	#define CONFIG_PHY_ADDR 0x1
	/*
	* GPIO configuration:
	* PSC1,2,3 predefined as UART
	* PCI disabled
	* Ethernet 100 with MD
	*/
	#define CFG_GPS_PORT_CONFIG 0x00058444

	/*
	* Miscellaneous configurable options
	*/
	#define CFG_LONGHELP /* undef to save memory */
	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	#else
	# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	#endif
	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	#define CFG_MAXARGS 16 /* max number of command args */
	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */

	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
	#define CFG_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */

	#define CFG_LOAD_ADDR 0x200000 /* default load address */

	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */

	#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */

	/*
	* Various low-level settings
	*/
	#define CFG_HID0_INIT HID0_ICE \| HID0_ICFI
	#define CFG_HID0_FINAL HID0_ICE

	#define CFG_BOOTCS_START CFG_FLASH_BASE
	#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
	#define CFG_BOOTCS_CFG 0x00047D01
	#define CFG_CS0_START CFG_FLASH_BASE
	#define CFG_CS0_SIZE CFG_FLASH_SIZE

	#define CFG_CS_BURST 0x00000000
	#define CFG_CS_DEADCYCLE 0x33333333

	#define CFG_RESET_ADDRESS 0x7f000000

	#endif /* __CONFIG_H */