| /* |
| * Copyright (C) 2011 Samsung Electronics |
| * |
| * SPDX-License-Identifier: GPL-2.0+ |
| */ |
| |
| #include <common.h> |
| #include <asm/io.h> |
| #include <netdev.h> |
| #include <asm/arch/cpu.h> |
| #include <asm/arch/gpio.h> |
| #include <asm/arch/mmc.h> |
| #include <asm/arch/periph.h> |
| #include <asm/arch/pinmux.h> |
| #include <asm/arch/sromc.h> |
| |
| DECLARE_GLOBAL_DATA_PTR; |
| |
| static void smc9115_pre_init(void) |
| { |
| u32 smc_bw_conf, smc_bc_conf; |
| |
| /* gpio configuration GPK0CON */ |
| gpio_cfg_pin(EXYNOS4_GPIO_Y00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2)); |
| |
| /* Ethernet needs bus width of 16 bits */ |
| smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK); |
| smc_bc_conf = SROMC_BC_TACS(0x0F) | SROMC_BC_TCOS(0x0F) |
| | SROMC_BC_TACC(0x0F) | SROMC_BC_TCOH(0x0F) |
| | SROMC_BC_TAH(0x0F) | SROMC_BC_TACP(0x0F) |
| | SROMC_BC_PMC(0x0F); |
| |
| /* Select and configure the SROMC bank */ |
| s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf); |
| } |
| |
| int board_init(void) |
| { |
| smc9115_pre_init(); |
| |
| gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); |
| return 0; |
| } |
| |
| int dram_init(void) |
| { |
| gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) |
| + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) |
| + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) |
| + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); |
| |
| return 0; |
| } |
| |
| void dram_init_banksize(void) |
| { |
| gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
| gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \ |
| PHYS_SDRAM_1_SIZE); |
| gd->bd->bi_dram[1].start = PHYS_SDRAM_2; |
| gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \ |
| PHYS_SDRAM_2_SIZE); |
| gd->bd->bi_dram[2].start = PHYS_SDRAM_3; |
| gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, \ |
| PHYS_SDRAM_3_SIZE); |
| gd->bd->bi_dram[3].start = PHYS_SDRAM_4; |
| gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, \ |
| PHYS_SDRAM_4_SIZE); |
| } |
| |
| int board_eth_init(bd_t *bis) |
| { |
| int rc = 0; |
| #ifdef CONFIG_SMC911X |
| rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); |
| #endif |
| return rc; |
| } |
| |
| #ifdef CONFIG_DISPLAY_BOARDINFO |
| int checkboard(void) |
| { |
| printf("\nBoard: SMDKV310\n"); |
| return 0; |
| } |
| #endif |
| |
| #ifdef CONFIG_GENERIC_MMC |
| int board_mmc_init(bd_t *bis) |
| { |
| int i, err; |
| |
| /* |
| * MMC2 SD card GPIO: |
| * |
| * GPK2[0] SD_2_CLK(2) |
| * GPK2[1] SD_2_CMD(2) |
| * GPK2[2] SD_2_CDn |
| * GPK2[3:6] SD_2_DATA[0:3](2) |
| */ |
| for (i = EXYNOS4_GPIO_K20; i < EXYNOS4_GPIO_K27; i++) { |
| /* GPK2[0:6] special function 2 */ |
| gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); |
| |
| /* GPK2[0:6] drv 4x */ |
| gpio_set_drv(i, S5P_GPIO_DRV_4X); |
| |
| /* GPK2[0:1] pull disable */ |
| if (i == EXYNOS4_GPIO_K20 || i == EXYNOS4_GPIO_K21) { |
| gpio_set_pull(i, S5P_GPIO_PULL_NONE); |
| continue; |
| } |
| |
| /* GPK2[2:6] pull up */ |
| gpio_set_pull(i, S5P_GPIO_PULL_UP); |
| } |
| err = s5p_mmc_init(2, 4); |
| return err; |
| } |
| #endif |
| |
| static int board_uart_init(void) |
| { |
| int err; |
| |
| err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE); |
| if (err) { |
| debug("UART0 not configured\n"); |
| return err; |
| } |
| |
| err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE); |
| if (err) { |
| debug("UART1 not configured\n"); |
| return err; |
| } |
| |
| err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE); |
| if (err) { |
| debug("UART2 not configured\n"); |
| return err; |
| } |
| |
| err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); |
| if (err) { |
| debug("UART3 not configured\n"); |
| return err; |
| } |
| |
| return 0; |
| } |
| |
| #ifdef CONFIG_BOARD_EARLY_INIT_F |
| int board_early_init_f(void) |
| { |
| int err; |
| err = board_uart_init(); |
| if (err) { |
| debug("UART init failed\n"); |
| return err; |
| } |
| return err; |
| } |
| #endif |