| CONFIG_SYS_FSL_ESDHC_LE means ESDHC IP is in little-endian mode. | |
| CONFIG_SYS_FSL_ESDHC_BE means ESDHC IP is in big-endian mode. | |
| CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT forces to run at 1.8V. | |
| Accessing ESDHC registers can be determined by ESDHC IP's endian | |
| mode or processor's endian mode. |