| /* |
| * (C) Copyright 2013 |
| * Texas Instruments Incorporated, <www.ti.com> |
| * |
| * Lokesh Vutla <lokeshvutla@ti.com> |
| * |
| * Based on previous work by: |
| * Aneesh V <aneesh@ti.com> |
| * Steve Sakoman <steve@sakoman.com> |
| * |
| * SPDX-License-Identifier: GPL-2.0+ |
| */ |
| #include <common.h> |
| #include <palmas.h> |
| #include <sata.h> |
| #include <asm/gpio.h> |
| #include <usb.h> |
| #include <linux/usb/gadget.h> |
| #include <asm/arch/gpio.h> |
| #include <asm/arch/dra7xx_iodelay.h> |
| #include <asm/arch/sys_proto.h> |
| #include <asm/arch/mmc_host_def.h> |
| #include <asm/arch/sata.h> |
| #include <environment.h> |
| #include <dwc3-uboot.h> |
| #include <dwc3-omap-uboot.h> |
| #include <ti-usb-phy-uboot.h> |
| |
| #include "mux_data.h" |
| |
| #ifdef CONFIG_DRIVER_TI_CPSW |
| #include <cpsw.h> |
| #endif |
| |
| DECLARE_GLOBAL_DATA_PTR; |
| |
| /* GPIO 7_11 */ |
| #define GPIO_DDR_VTT_EN 203 |
| |
| const struct omap_sysinfo sysinfo = { |
| "Board: DRA7xx\n" |
| }; |
| |
| /** |
| * @brief board_init |
| * |
| * @return 0 |
| */ |
| int board_init(void) |
| { |
| gpmc_init(); |
| gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ |
| |
| return 0; |
| } |
| |
| int board_late_init(void) |
| { |
| #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
| u32 id[4]; |
| |
| if (omap_revision() == DRA722_ES1_0) |
| setenv("board_name", "dra72x"); |
| else |
| setenv("board_name", "dra7xx"); |
| |
| id[0] = readl((*ctrl)->control_std_fuse_die_id_0); |
| id[1] = readl((*ctrl)->control_std_fuse_die_id_1); |
| usb_set_serial_num_from_die_id(id); |
| #endif |
| return 0; |
| } |
| |
| void set_muxconf_regs_essential(void) |
| { |
| do_set_mux32((*ctrl)->control_padconf_core_base, |
| early_padconf, ARRAY_SIZE(early_padconf)); |
| } |
| |
| #ifdef CONFIG_IODELAY_RECALIBRATION |
| void recalibrate_iodelay(void) |
| { |
| struct pad_conf_entry const *pads; |
| struct iodelay_cfg_entry const *iodelay; |
| int npads, niodelays; |
| |
| switch (omap_revision()) { |
| case DRA722_ES1_0: |
| pads = core_padconf_array_essential; |
| npads = ARRAY_SIZE(core_padconf_array_essential); |
| iodelay = iodelay_cfg_array; |
| niodelays = ARRAY_SIZE(iodelay_cfg_array); |
| break; |
| case DRA752_ES1_0: |
| case DRA752_ES1_1: |
| pads = dra74x_core_padconf_array; |
| npads = ARRAY_SIZE(dra74x_core_padconf_array); |
| iodelay = dra742_es1_1_iodelay_cfg_array; |
| niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array); |
| break; |
| default: |
| case DRA752_ES2_0: |
| pads = dra74x_core_padconf_array; |
| npads = ARRAY_SIZE(dra74x_core_padconf_array); |
| iodelay = dra742_es2_0_iodelay_cfg_array; |
| niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array); |
| /* Setup port1 and port2 for rgmii with 'no-id' mode */ |
| clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK | |
| RGMII1_ID_MODE_N_MASK); |
| break; |
| } |
| __recalibrate_iodelay(pads, npads, iodelay, niodelays); |
| } |
| #endif |
| |
| #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) |
| int board_mmc_init(bd_t *bis) |
| { |
| omap_mmc_init(0, 0, 0, -1, -1); |
| omap_mmc_init(1, 0, 0, -1, -1); |
| return 0; |
| } |
| #endif |
| |
| #ifdef CONFIG_USB_DWC3 |
| static struct dwc3_device usb_otg_ss1 = { |
| .maximum_speed = USB_SPEED_SUPER, |
| .base = DRA7_USB_OTG_SS1_BASE, |
| .tx_fifo_resize = false, |
| .index = 0, |
| }; |
| |
| static struct dwc3_omap_device usb_otg_ss1_glue = { |
| .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE, |
| .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, |
| .index = 0, |
| }; |
| |
| static struct ti_usb_phy_device usb_phy1_device = { |
| .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL, |
| .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER, |
| .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER, |
| .index = 0, |
| }; |
| |
| static struct dwc3_device usb_otg_ss2 = { |
| .maximum_speed = USB_SPEED_SUPER, |
| .base = DRA7_USB_OTG_SS2_BASE, |
| .tx_fifo_resize = false, |
| .index = 1, |
| }; |
| |
| static struct dwc3_omap_device usb_otg_ss2_glue = { |
| .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE, |
| .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, |
| .index = 1, |
| }; |
| |
| static struct ti_usb_phy_device usb_phy2_device = { |
| .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER, |
| .index = 1, |
| }; |
| |
| int board_usb_init(int index, enum usb_init_type init) |
| { |
| enable_usb_clocks(index); |
| switch (index) { |
| case 0: |
| if (init == USB_INIT_DEVICE) { |
| usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL; |
| usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; |
| } else { |
| usb_otg_ss1.dr_mode = USB_DR_MODE_HOST; |
| usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; |
| } |
| |
| ti_usb_phy_uboot_init(&usb_phy1_device); |
| dwc3_omap_uboot_init(&usb_otg_ss1_glue); |
| dwc3_uboot_init(&usb_otg_ss1); |
| break; |
| case 1: |
| if (init == USB_INIT_DEVICE) { |
| usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; |
| usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; |
| } else { |
| usb_otg_ss2.dr_mode = USB_DR_MODE_HOST; |
| usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; |
| } |
| |
| ti_usb_phy_uboot_init(&usb_phy2_device); |
| dwc3_omap_uboot_init(&usb_otg_ss2_glue); |
| dwc3_uboot_init(&usb_otg_ss2); |
| break; |
| default: |
| printf("Invalid Controller Index\n"); |
| } |
| |
| return 0; |
| } |
| |
| int board_usb_cleanup(int index, enum usb_init_type init) |
| { |
| switch (index) { |
| case 0: |
| case 1: |
| ti_usb_phy_uboot_exit(index); |
| dwc3_uboot_exit(index); |
| dwc3_omap_uboot_exit(index); |
| break; |
| default: |
| printf("Invalid Controller Index\n"); |
| } |
| disable_usb_clocks(index); |
| return 0; |
| } |
| |
| int usb_gadget_handle_interrupts(int index) |
| { |
| u32 status; |
| |
| status = dwc3_omap_uboot_interrupt_status(index); |
| if (status) |
| dwc3_uboot_handle_interrupt(index); |
| |
| return 0; |
| } |
| #endif |
| |
| #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) |
| int spl_start_uboot(void) |
| { |
| /* break into full u-boot on 'c' */ |
| if (serial_tstc() && serial_getc() == 'c') |
| return 1; |
| |
| #ifdef CONFIG_SPL_ENV_SUPPORT |
| env_init(); |
| env_relocate_spec(); |
| if (getenv_yesno("boot_os") != 1) |
| return 1; |
| #endif |
| |
| return 0; |
| } |
| #endif |
| |
| #ifdef CONFIG_DRIVER_TI_CPSW |
| extern u32 *const omap_si_rev; |
| |
| static void cpsw_control(int enabled) |
| { |
| /* VTP can be added here */ |
| |
| return; |
| } |
| |
| static struct cpsw_slave_data cpsw_slaves[] = { |
| { |
| .slave_reg_ofs = 0x208, |
| .sliver_reg_ofs = 0xd80, |
| .phy_addr = 2, |
| }, |
| { |
| .slave_reg_ofs = 0x308, |
| .sliver_reg_ofs = 0xdc0, |
| .phy_addr = 3, |
| }, |
| }; |
| |
| static struct cpsw_platform_data cpsw_data = { |
| .mdio_base = CPSW_MDIO_BASE, |
| .cpsw_base = CPSW_BASE, |
| .mdio_div = 0xff, |
| .channels = 8, |
| .cpdma_reg_ofs = 0x800, |
| .slaves = 2, |
| .slave_data = cpsw_slaves, |
| .ale_reg_ofs = 0xd00, |
| .ale_entries = 1024, |
| .host_port_reg_ofs = 0x108, |
| .hw_stats_reg_ofs = 0x900, |
| .bd_ram_ofs = 0x2000, |
| .mac_control = (1 << 5), |
| .control = cpsw_control, |
| .host_port_num = 0, |
| .version = CPSW_CTRL_VERSION_2, |
| }; |
| |
| int board_eth_init(bd_t *bis) |
| { |
| int ret; |
| uint8_t mac_addr[6]; |
| uint32_t mac_hi, mac_lo; |
| uint32_t ctrl_val; |
| |
| /* try reading mac address from efuse */ |
| mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); |
| mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); |
| mac_addr[0] = (mac_hi & 0xFF0000) >> 16; |
| mac_addr[1] = (mac_hi & 0xFF00) >> 8; |
| mac_addr[2] = mac_hi & 0xFF; |
| mac_addr[3] = (mac_lo & 0xFF0000) >> 16; |
| mac_addr[4] = (mac_lo & 0xFF00) >> 8; |
| mac_addr[5] = mac_lo & 0xFF; |
| |
| if (!getenv("ethaddr")) { |
| printf("<ethaddr> not set. Validating first E-fuse MAC\n"); |
| |
| if (is_valid_ethaddr(mac_addr)) |
| eth_setenv_enetaddr("ethaddr", mac_addr); |
| } |
| |
| mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); |
| mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); |
| mac_addr[0] = (mac_hi & 0xFF0000) >> 16; |
| mac_addr[1] = (mac_hi & 0xFF00) >> 8; |
| mac_addr[2] = mac_hi & 0xFF; |
| mac_addr[3] = (mac_lo & 0xFF0000) >> 16; |
| mac_addr[4] = (mac_lo & 0xFF00) >> 8; |
| mac_addr[5] = mac_lo & 0xFF; |
| |
| if (!getenv("eth1addr")) { |
| if (is_valid_ethaddr(mac_addr)) |
| eth_setenv_enetaddr("eth1addr", mac_addr); |
| } |
| |
| ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); |
| ctrl_val |= 0x22; |
| writel(ctrl_val, (*ctrl)->control_core_control_io1); |
| |
| if (*omap_si_rev == DRA722_ES1_0) |
| cpsw_data.active_slave = 1; |
| |
| ret = cpsw_register(&cpsw_data); |
| if (ret < 0) |
| printf("Error %d registering CPSW switch\n", ret); |
| |
| return ret; |
| } |
| #endif |
| |
| #ifdef CONFIG_BOARD_EARLY_INIT_F |
| /* VTT regulator enable */ |
| static inline void vtt_regulator_enable(void) |
| { |
| if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) |
| return; |
| |
| /* Do not enable VTT for DRA722 */ |
| if (omap_revision() == DRA722_ES1_0) |
| return; |
| |
| /* |
| * EVM Rev G and later use gpio7_11 for DDR3 termination. |
| * This is safe enough to do on older revs. |
| */ |
| gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); |
| gpio_direction_output(GPIO_DDR_VTT_EN, 1); |
| } |
| |
| int board_early_init_f(void) |
| { |
| vtt_regulator_enable(); |
| return 0; |
| } |
| #endif |