blob: 1c6032c2547773428fd779f2fcbb4718d6ee15f6 [file] [log] [blame]
Jan Kundrát04d102b2017-10-19 12:04:06 +02001diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c
Jan Kundrát6fa87502018-01-12 15:09:58 +01002index 1472e9793e..2b365793fb 100644
Jan Kundrát04d102b2017-10-19 12:04:06 +02003--- a/board/solidrun/clearfog/clearfog.c
4+++ b/board/solidrun/clearfog/clearfog.c
5@@ -11,10 +11,15 @@
6 #include <asm/io.h>
7 #include <asm/arch/cpu.h>
8 #include <asm/arch/soc.h>
9+#include <dm/uclass.h>
10
11 #include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
12 #include <../serdes/a38x/high_speed_env_spec.h>
13
14+#ifdef CONFIG_WDT_ORION
15+# include <wdt.h>
16+#endif
17+
18 DECLARE_GLOBAL_DATA_PTR;
19
20 #define ETH_PHY_CTRL_REG 0
21@@ -122,6 +127,10 @@ int board_early_init_f(void)
22 return 0;
23 }
24
25+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION)
26+static struct udevice *watchdog_dev = NULL;
27+#endif
28+
29 int board_init(void)
30 {
31 int i;
32@@ -129,6 +138,18 @@ int board_init(void)
33 /* Address of boot parameters */
34 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
35
36+#ifndef CONFIG_SPL_BUILD
37+# ifdef CONFIG_WDT_ORION
38+ if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
39+ puts("Cannot find Armada 385 watchdog!\n");
40+ } else {
41+ puts("Enabling Armada 385 watchdog.\n");
42+ /* one minute */
43+ wdt_start(watchdog_dev, (u32) 25000000 * 60, 0);
44+ }
45+# endif
46+#endif
47+
48 /* Toggle GPIO41 to reset onboard switch and phy */
49 clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
50 clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9));
51@@ -147,6 +168,28 @@ int board_init(void)
52 return 0;
53 }
54
55+#ifdef CONFIG_WATCHDOG
56+/* Called by macro WATCHDOG_RESET */
57+void watchdog_reset(void)
58+{
59+# if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION)
60+ static ulong next_reset = 0;
61+ ulong now;
62+
63+ if (!watchdog_dev)
64+ return;
65+
66+ now = timer_get_us();
67+
68+ /* Do not reset the watchdog too often */
69+ if (now > next_reset) {
70+ wdt_reset(watchdog_dev);
71+ next_reset = now + 1000;
72+ }
73+# endif
74+}
75+#endif
76+
77 int checkboard(void)
78 {
79 puts("Board: SolidRun ClearFog\n");
80diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig
Jan Kundrát6fa87502018-01-12 15:09:58 +010081index 7161518715..4d4f96241c 100644
Jan Kundrát04d102b2017-10-19 12:04:06 +020082--- a/configs/clearfog_defconfig
83+++ b/configs/clearfog_defconfig
Jan Kundrát6fa87502018-01-12 15:09:58 +010084@@ -48,3 +48,5 @@ CONFIG_USB=y
Jan Kundrát04d102b2017-10-19 12:04:06 +020085 CONFIG_DM_USB=y
Jan Kundrát6fa87502018-01-12 15:09:58 +010086 CONFIG_USB_XHCI_HCD=y
Jan Kundrát04d102b2017-10-19 12:04:06 +020087 CONFIG_USB_STORAGE=y
88+CONFIG_WDT=y
89+CONFIG_WDT_ORION=y
90diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h
Jan Kundrát6fa87502018-01-12 15:09:58 +010091index bf87bac300..4c5ac5b075 100644
Jan Kundrát04d102b2017-10-19 12:04:06 +020092--- a/include/configs/clearfog.h
93+++ b/include/configs/clearfog.h
94@@ -32,6 +32,11 @@
95 #define CONFIG_SYS_I2C_SLAVE 0x0
96 #define CONFIG_SYS_I2C_SPEED 100000
97
98+/* Watchdog */
99+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION)
100+# define CONFIG_WATCHDOG
101+#endif
102+
103 /* SPI NOR flash default params, used by sf commands */
Jan Kundrát6fa87502018-01-12 15:09:58 +0100104 #define CONFIG_SF_DEFAULT_BUS 1
105
106@@ -63,6 +68,9 @@
Jan Kundrát04d102b2017-10-19 12:04:06 +0200107 #define CONFIG_ENV_OFFSET 0xf0000
108 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
109
110+#define CONFIG_ENV_OFFSET_REDUND 0xe0000
111+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
112+
113 #define CONFIG_PHY_MARVELL /* there is a marvell phy */
114 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
115
Jan Kundrát6fa87502018-01-12 15:09:58 +0100116@@ -161,17 +169,47 @@
117 "kernel_addr_r=" KERNEL_ADDR_R "\0" \
118 "fdt_addr_r=" FDT_ADDR_R "\0" \
119 "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \
120- "scriptaddr=" SCRIPT_ADDR_R "\0" \
121+ "script_addr_r=" SCRIPT_ADDR_R "\0" \
Jan Kundrát04d102b2017-10-19 12:04:06 +0200122 "pxefile_addr_r=" PXEFILE_ADDR_R "\0"
123
124-#include <config_distro_bootcmd.h>
125-
126 #define CONFIG_EXTRA_ENV_SETTINGS \
127 RELOCATION_LIMITS_ENV_SETTINGS \
128 LOAD_ADDRESS_ENV_SETTINGS \
129- "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
130 "console=ttyS0,115200\0" \
131- BOOTENV
Jan Kundrát04d102b2017-10-19 12:04:06 +0200132+ "bootcmd=test -n \"${BOOT_A_LEFT}\" || setenv BOOT_A_LEFT 3;" \
133+ "test -n \"${BOOT_B_LEFT}\" || setenv BOOT_B_LEFT 3;" \
Jan Kundráta98768a2017-10-20 17:08:23 +0200134+ "test -n \"${BOOT_ORDER}\" || setenv BOOT_ORDER \"A B\";" \
Jan Kundrát04d102b2017-10-19 12:04:06 +0200135+ "setenv rauc_part;" \
Jan Kundráta98768a2017-10-20 17:08:23 +0200136+ "for BOOT_SLOT in \"${BOOT_ORDER}\"; do" \
Jan Kundrát04d102b2017-10-19 12:04:06 +0200137+ " if test \"x${rauc_part}\" != \"x\"; then" \
138+ " ;" \
139+ " elif test \"x${BOOT_SLOT}\" = \"xA\"; then" \
140+ " if test ${BOOT_A_LEFT} -gt 0; then" \
141+ " setexpr BOOT_A_LEFT ${BOOT_A_LEFT} - 1;" \
142+ " echo \"Found valid slot A, ${BOOT_A_LEFT} attempts remaining\";" \
143+ " setenv rauc_part 1;" \
144+ " setenv rauc_slot A;" \
145+ " fi;" \
146+ " elif test \"x${BOOT_SLOT}\" = \"xB\"; then" \
147+ " if test ${BOOT_B_LEFT} -gt 0; then" \
148+ " setexpr BOOT_B_LEFT ${BOOT_B_LEFT} - 1;" \
149+ " echo \"Found valid slot B, ${BOOT_B_LEFT} attempts remaining\";" \
Jan Kundrátb425ea82017-10-19 17:56:36 +0200150+ " setenv rauc_part 3;" \
Jan Kundrát04d102b2017-10-19 12:04:06 +0200151+ " setenv rauc_slot B;" \
152+ " fi;" \
153+ " fi;" \
154+ "done;" \
155+ "if test -n \"${rauc_part}\"; then" \
156+ " saveenv ;" \
157+ "else" \
158+ " echo \"No valid slot found, resetting tries to 3\";" \
159+ " setenv BOOT_A_LEFT 3;" \
160+ " setenv BOOT_B_LEFT 3;" \
161+ " saveenv;" \
162+ " reset;" \
163+ "fi;" \
Jan Kundrát6fa87502018-01-12 15:09:58 +0100164+ "load mmc 0:${rauc_part} ${script_addr_r} /boot/boot.scr || reset;" \
165+ "source ${script_addr_r} || reset\0"
Jan Kundrát04d102b2017-10-19 12:04:06 +0200166
167 #endif /* CONFIG_SPL_BUILD */
168