| diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt |
| index 8b94aa8f5971..2723e6143aa9 100644 |
| --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt |
| +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt |
| @@ -144,3 +144,38 @@ gpio21: gpio@21 { |
| bias-pull-up; |
| }; |
| }; |
| + |
| +Line naming |
| +=========== |
| + |
| +Because several gpio_chip instances are hidden below a single device tree |
| +node, it is necessary to split the names into several child nodes. Ensure |
| +that the configured addresses match those in the microchip,spi-present-mask: |
| + |
| +gpio@0 { |
| + compatible = "microchip,mcp23s17"; |
| + gpio-controller; |
| + #gpio-cells = <2>; |
| + /* this bitmask has bits #0 (0x01) and #2 (0x04) set */ |
| + spi-present-mask = <0x05>; |
| + reg = <0>; |
| + spi-max-frequency = <1000000>; |
| + |
| + gpio-bank@1 { |
| + address = <0>; |
| + gpio-line-names = |
| + "GPA0", |
| + "GPA1", |
| + ... |
| + "GPA7", |
| + "GPB0", |
| + "GPB1", |
| + ... |
| + "GPB7"; |
| + }; |
| + |
| + gpio-bank@2 { |
| + address = <2>; |
| + gpio-line-names = ... |
| + }; |
| +}; |
| diff --git a/drivers/leds/leds-tlc591xx.c b/drivers/leds/leds-tlc591xx.c |
| index 59ff088c7d75..c7c6f753b0d3 100644 |
| --- a/drivers/leds/leds-tlc591xx.c |
| +++ b/drivers/leds/leds-tlc591xx.c |
| @@ -39,6 +39,9 @@ |
| |
| #define ldev_to_led(c) container_of(c, struct tlc591xx_led, ldev) |
| |
| +#define TLC591XX_RESET_BYTE_0 0xa5 |
| +#define TLC591XX_RESET_BYTE_1 0x5a |
| + |
| struct tlc591xx_led { |
| bool active; |
| unsigned int led_no; |
| @@ -50,21 +53,25 @@ struct tlc591xx_priv { |
| struct tlc591xx_led leds[TLC591XX_MAX_LEDS]; |
| struct regmap *regmap; |
| unsigned int reg_ledout_offset; |
| + struct i2c_client *swrst_client; |
| }; |
| |
| struct tlc591xx { |
| unsigned int max_leds; |
| unsigned int reg_ledout_offset; |
| + u8 swrst_addr; |
| }; |
| |
| static const struct tlc591xx tlc59116 = { |
| .max_leds = 16, |
| .reg_ledout_offset = 0x14, |
| + .swrst_addr = 0x6b, |
| }; |
| |
| static const struct tlc591xx tlc59108 = { |
| .max_leds = 8, |
| .reg_ledout_offset = 0x0c, |
| + .swrst_addr = 0x4b, |
| }; |
| |
| static int |
| @@ -137,6 +144,8 @@ tlc591xx_destroy_devices(struct tlc591xx_priv *priv, unsigned int j) |
| if (priv->leds[i].active) |
| led_classdev_unregister(&priv->leds[i].ldev); |
| } |
| + |
| + i2c_unregister_device(priv->swrst_client); |
| } |
| |
| static int |
| @@ -242,6 +251,19 @@ tlc591xx_probe(struct i2c_client *client, |
| priv->leds[reg].ldev.default_trigger = |
| of_get_property(child, "linux,default-trigger", NULL); |
| } |
| + |
| + priv->swrst_client = i2c_new_dummy(client->adapter, tlc591xx->swrst_addr); |
| + if (priv->swrst_client) { |
| + err = i2c_smbus_write_byte_data(priv->swrst_client, |
| + TLC591XX_RESET_BYTE_0, TLC591XX_RESET_BYTE_1); |
| + if (err) { |
| + dev_warn(dev, "SW reset failed\n"); |
| + } |
| + } else { |
| + dev_info(dev, "Skipping reset: address %02x already used\n", |
| + tlc591xx->swrst_addr); |
| + } |
| + |
| return tlc591xx_configure(dev, priv, tlc591xx); |
| } |
| |
| diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c |
| index 3a235487e38d..3358891b3ea2 100644 |
| --- a/drivers/pinctrl/pinctrl-mcp23s08.c |
| +++ b/drivers/pinctrl/pinctrl-mcp23s08.c |
| @@ -993,6 +993,7 @@ static int mcp23s08_probe(struct spi_device *spi) |
| int status, type; |
| unsigned ngpio = 0; |
| const struct of_device_id *match; |
| + struct device_node *np; |
| |
| match = of_match_device(of_match_ptr(mcp23s08_spi_of_match), &spi->dev); |
| if (match) |
| @@ -1061,6 +1062,16 @@ static int mcp23s08_probe(struct spi_device *spi) |
| if (pdata->base != -1) |
| pdata->base += data->mcp[addr]->chip.ngpio; |
| ngpio += data->mcp[addr]->chip.ngpio; |
| + |
| + for_each_available_child_of_node(spi->dev.of_node, np) { |
| + u32 chip_addr; |
| + status = of_property_read_u32(np, "address", &chip_addr); |
| + if (status) |
| + continue; |
| + if (chip_addr != addr) |
| + continue; |
| + devprop_gpiochip_set_names(&data->mcp[addr]->chip, of_fwnode_handle(np)); |
| + } |
| } |
| data->ngpio = ngpio; |
| |
| diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c |
| index 6643ccdc2508..d7ec35233d7e 100644 |
| --- a/drivers/spi/spi-orion.c |
| +++ b/drivers/spi/spi-orion.c |
| @@ -88,10 +88,6 @@ struct orion_direct_acc { |
| u32 size; |
| }; |
| |
| -struct orion_child_options { |
| - struct orion_direct_acc direct_access; |
| -}; |
| - |
| struct orion_spi { |
| struct spi_master *master; |
| void __iomem *base; |
| @@ -100,7 +96,7 @@ struct orion_spi { |
| const struct orion_spi_dev *devdata; |
| int unused_hw_gpio; |
| |
| - struct orion_child_options child[ORION_NUM_CHIPSELECTS]; |
| + struct orion_direct_acc direct_access[ORION_NUM_CHIPSELECTS]; |
| }; |
| |
| static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg) |
| @@ -430,7 +426,7 @@ orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer) |
| int cs = spi->chip_select; |
| void __iomem *vaddr; |
| |
| - word_len = spi->bits_per_word; |
| + word_len = xfer->bits_per_word; |
| count = xfer->len; |
| |
| orion_spi = spi_master_get_devdata(spi->master); |
| @@ -439,7 +435,7 @@ orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer) |
| * Use SPI direct write mode if base address is available. Otherwise |
| * fall back to PIO mode for this transfer. |
| */ |
| - vaddr = orion_spi->child[cs].direct_access.vaddr; |
| + vaddr = orion_spi->direct_access[cs].vaddr; |
| |
| if (vaddr && xfer->tx_buf && word_len == 8) { |
| unsigned int cnt = count / 4; |
| @@ -684,7 +680,6 @@ static int orion_spi_probe(struct platform_device *pdev) |
| } |
| |
| for_each_available_child_of_node(pdev->dev.of_node, np) { |
| - struct orion_direct_acc *dir_acc; |
| u32 cs; |
| int cs_gpio; |
| |
| @@ -752,13 +747,14 @@ static int orion_spi_probe(struct platform_device *pdev) |
| * This needs to get extended for the direct SPI-NOR / SPI-NAND |
| * support, once this gets implemented. |
| */ |
| - dir_acc = &spi->child[cs].direct_access; |
| - dir_acc->vaddr = devm_ioremap(&pdev->dev, r->start, PAGE_SIZE); |
| - if (!dir_acc->vaddr) { |
| + spi->direct_access[cs].vaddr = devm_ioremap(&pdev->dev, |
| + r->start, |
| + PAGE_SIZE); |
| + if (!spi->direct_access[cs].vaddr) { |
| status = -ENOMEM; |
| goto out_rel_axi_clk; |
| } |
| - dir_acc->size = PAGE_SIZE; |
| + spi->direct_access[cs].size = PAGE_SIZE; |
| |
| dev_info(&pdev->dev, "CS%d configured for direct access\n", cs); |
| } |
| diff --git a/drivers/tty/serial/max310x.c b/drivers/tty/serial/max310x.c |
| index 8434bd5a8ec7..59d3c27d36a2 100644 |
| --- a/drivers/tty/serial/max310x.c |
| +++ b/drivers/tty/serial/max310x.c |
| @@ -235,6 +235,10 @@ |
| #define MAX310x_REV_MASK (0xf8) |
| #define MAX310X_WRITE_BIT 0x80 |
| |
| +/* Timeout for external crystal stability */ |
| +#define MAX310X_XTAL_WAIT_RETRIES 20 |
| +#define MAX310X_XTAL_WAIT_DELAY_MS 10 |
| + |
| /* MAX3107 specific */ |
| #define MAX3107_REV_ID (0xa0) |
| |
| @@ -610,11 +614,14 @@ static int max310x_set_ref_clk(struct device *dev, struct max310x_port *s, |
| |
| /* Wait for crystal */ |
| if (xtal) { |
| - unsigned int val; |
| - msleep(10); |
| - regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val); |
| + unsigned int val = 0, i; |
| + for (i = 0; i < MAX310X_XTAL_WAIT_RETRIES && !(val & MAX310X_STS_CLKREADY_BIT); ++i) { |
| + msleep(MAX310X_XTAL_WAIT_DELAY_MS); |
| + regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val); |
| + } |
| if (!(val & MAX310X_STS_CLKREADY_BIT)) { |
| - dev_warn(dev, "clock is not stable yet\n"); |
| + dev_err(dev, "clock is not stable\n"); |
| + return -EAGAIN; |
| } |
| } |
| |
| @@ -1327,6 +1334,10 @@ static int max310x_probe(struct device *dev, struct max310x_devtype *devtype, |
| } |
| |
| uartclk = max310x_set_ref_clk(dev, s, freq, xtal); |
| + if (uartclk < 0) { |
| + ret = uartclk; |
| + goto out_uart; |
| + } |
| dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk); |
| |
| for (i = 0; i < devtype->nr; i++) { |