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gerrit.cesnet.cz / github / trini / u-boot / fffe25db04b428f34b72264ff50c40f395fcd936 / drivers / ddr / fsl / main.c
  1. 5b8031c Add more SPDX-License-Identifier tags by Tom Rini · 9 years ago
  2. 61bd2f7 drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3 by York Sun · 9 years ago
  3. 5684842 drivers/ddr/fsl: Adjust bstopre value by York Sun · 9 years ago
  4. b92557c driver/ddr/fsl: Add a hook to update SPD address by York Sun · 9 years ago
  5. 66869f9 drivers/ddr/fsl: Update DDR driver for DDR4 by York Sun · 10 years ago
  6. e32d59a driver/ddr/fsl: Add sync of refresh by York Sun · 10 years ago
  7. 03e664d driver/ddr/fsl: Add support for multiple DDR clocks by York Sun · 10 years ago
  8. b414119 linux/kernel.h: sync min, max, min3, max3 macros with Linux by Masahiro Yamada · 10 years ago
  9. 1d71efb driver/ddr: Restruct driver to allow standalone memory space by York Sun · 10 years ago
  10. 349689b drivers/ddr: Fix possible out of bounds error by York Sun · 11 years ago
  11. 34e026f driver/ddr/fsl: Add DDR4 support to Freescale DDR driver by York Sun · 11 years ago
  12. 6b1e125 driver/ddr: Add 256 byte interleaving support by York Sun · 11 years ago
  13. 6b9e309 Driver/ddr: Add support of different DDR base address by York Sun · 11 years ago
  14. 00ec3fd Driver/DDR: Update DDR driver to allow non-zero base address by York Sun · 11 years ago
  15. 9ac4ffb Driver/DDR: Add Freescale DDR driver for ARM by York Sun · 11 years ago
  16. 5614e71 Driver/DDR: Moving Freescale DDR driver to a common driver by York Sun · 11 years ago[Renamed (99%) from arch/powerpc/cpu/mpc8xxx/ddr/main.c]
  17. 0778bbe mpc8xxx: call i2c_set_bus_num in __get_spd by Valentin Longchamp · 11 years ago
  18. 0dd38a3 powerpc: Fix CamelCase warnings in DDR related code by Priyanka Jain · 11 years ago
  19. 2f848f9 powerpc: Use print_size() where appropriate by Shruti Kanetkar · 11 years ago
  20. c63e137 powerpc/mpc8xxx: Add memory reset control by York Sun · 11 years ago
  21. d8556db powerpc/mpc8xxx: Set inactive csn_bnds to 0xffffffff by York Sun · 11 years ago
  22. ef00227 powerpc/mpc8xxx: Allow board file to override DDR address assignment by York Sun · 12 years ago
  23. 0a7c535 powerpc/mpc8xxx: Fix DDR 3-way interleaving by York Sun · 12 years ago
  24. e8ba6c5 powerpc/mpc8xxxx: FSL DDR debugger auto run of stored commands by James Yang · 12 years ago
  25. e750cfa powerpc/mpc8xxx: Enable entering DDR debugging by key press by York Sun · 12 years ago
  26. 82968a7 powerpc/mpc8xxx: Fix DDR SPD failed message by York Sun · 12 years ago
  27. f31cfd1 powerpc/mpc8xxx: Fix DDR initialization waiting for D_INIT by York Sun · 12 years ago
  28. 62f739f powerpc/mpc8xxx DDR: Fall back to raw timing for first controller only by York Sun · 12 years ago
  29. a4c6650 powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving by York Sun · 12 years ago
  30. 98de369 powerpc/ddr: fix fsl_ddr_get_dimm_params compile error by Shaohui Xie · 12 years ago
  31. 6f5e1dc powerpc/8xxx: Add support for interactive DDR programming interface by York Sun · 13 years ago
  32. 639f330 powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slots by York Sun · 13 years ago
  33. f2d264b powerpc/mpc8xxx: Adding fallback to raw timing on supported boards by York Sun · 13 years ago
  34. 1b3e3c4 powerpc/mpc8xxx: Enable calculation for fixed DDR chips by York Sun · 13 years ago
  35. 51d498f powerpc/mpc8xxx: Add 16-bit support for DDR3 by York Sun · 13 years ago
  36. c39f44d powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from board by Kumar Gala · 14 years ago
  37. fc0c2b6 8xxx/ddr: add support to only compute the ddr sdram size by Haiying Wang · 14 years ago
  38. 7ea3871 MPC8xxx DDR: align informational prints by Becky Bruce · 14 years ago
  39. 076bff8 powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4 by york · 14 years ago
  40. a47a12b Move arch/ppc to arch/powerpc by Stefan Roese · 15 years ago[Renamed from arch/ppc/cpu/mpc8xxx/ddr/main.c]
  41. 8d1f268 ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU by Peter Tyser · 15 years ago[Renamed from cpu/mpc8xxx/ddr/main.c]
  42. d9c147f 85xx, 86xx: Add common board_add_ram_info() by Peter Tyser · 15 years ago
  43. e7563af fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT by Kumar Gala · 15 years ago
  44. edf0e25 fsl-ddr: Allow system to boot if we have more than 4G of memory by Kumar Gala · 16 years ago
  45. 7008d26 fsl ddr skip interleaving if not supported. by Ed Swarthout · 16 years ago
  46. c9ffd83 Check DDR interleaving mode by Haiying Wang · 16 years ago
  47. dfb4910 Pass dimm parameters to populate populate controller options by Haiying Wang · 16 years ago
  48. dbbbb3a Make DDR interleaving mode work correctly by Haiying Wang · 16 years ago
  49. f12e454 Coding style cleanup, update CHANGELOG by Wolfgang Denk · 16 years ago
  50. 58e5e9a FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · 16 years ago