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gerrit.cesnet.cz / github / trini / u-boot / fd8f4729ac6520e59dd1d3f57d503d8abe345ac5 / arch / x86 / cpu / ivybridge / cpu.c
  1. 7b95252 x86: chromebook_link: Enable the debug UART by Simon Glass · 9 years ago
  2. 5021c81 x86: ivybridge: Use reset_cpu() by Simon Glass · 10 years ago
  3. 90b16d1 x86: chromebook_link: dts: Add PCH and LPC devices by Simon Glass · 10 years ago
  4. aad78d2 dm: x86: pci: Convert chromebook_link to use driver model for pci by Simon Glass · 10 years ago
  5. 161d2e4 x86: Split up arch_cpu_init() by Simon Glass · 10 years ago
  6. 31f57c2 x86: Add a x86_ prefix to the x86-specific PCI functions by Simon Glass · 10 years ago
  7. c72f74e x86: ivybridge: Update microcode early in boot by Simon Glass · 10 years ago
  8. 3a5659f x86: ivybridge: Drop support for ROM caching by Simon Glass · 10 years ago
  9. 95a5a47 x86: Add post failure codes for bist and car by Bin Meng · 10 years ago
  10. 3eafce0 x86: ivybridge: Add LAPIC support by Simon Glass · 10 years ago
  11. 8e0df06 x86: ivybridge: Add early init for PCH devices by Simon Glass · 10 years ago
  12. 77f9b1f x86: ivybridge: Perform Intel microcode update on boot by Simon Glass · 10 years ago
  13. 94060ff x86: ivybridge: Check BIST value on boot by Simon Glass · 10 years ago
  14. f5fbbe9 x86: ivybridge: Perform initial CPU setup by Simon Glass · 10 years ago
  15. 2b60515 x86: ivybridge: Add early LPC init so that serial works by Simon Glass · 10 years ago
  16. 6e5b12b x86: ivybridge: Enable PCI in early init by Simon Glass · 10 years ago
  17. 70a09c6 x86: chromebook_link: Implement CAR support (cache as RAM) by Simon Glass · 10 years ago
  18. 8ef0757 x86: Add chromebook_link board by Simon Glass · 10 years ago