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gerrit.cesnet.cz / github / trini / u-boot / fc01ea1e27d5b124f0a1868d0ce569f156d58dfe / cpu / mpc8xxx / ddr
  1. b4983e1 fsl-ddr: use the 1T timing as default configuration by Dave Liu · 16 years ago
  2. 22cca7e fsl-ddr: make the self refresh idle threshold configurable by Dave Liu · 16 years ago
  3. 22ff3d0 fsl-ddr: clean up the ddr code for DDR3 controller by Dave Liu · 16 years ago
  4. 80ee3ce fsl-ddr: update the bit mask for DDR3 controller by Dave Liu · 16 years ago
  5. 7008d26 fsl ddr skip interleaving if not supported. by Ed Swarthout · 16 years ago
  6. 1f293b4 Add debug information for DDR controller registers by Haiying Wang · 16 years ago
  7. c9ffd83 Check DDR interleaving mode by Haiying Wang · 16 years ago
  8. dfb4910 Pass dimm parameters to populate populate controller options by Haiying Wang · 16 years ago
  9. dbbbb3a Make DDR interleaving mode work correctly by Haiying Wang · 16 years ago
  10. 6d0f6bc rename CFG_ macros to CONFIG_SYS by Jean-Christophe PLAGNIOL-VILLARD · 16 years ago
  11. f12e454 Coding style cleanup, update CHANGELOG by Wolfgang Denk · 16 years ago
  12. 302e52e Fix compiler warning in mpc8xxx ddr code by Kumar Gala · 16 years ago
  13. 233fdd5 FSL DDR: Add DDR2 DIMM paramter support by Kumar Gala · 16 years ago
  14. 05c05a2 FSL DDR: Add DDR1 DIMM paramter support by Kumar Gala · 16 years ago
  15. 58e5e9a FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · 16 years ago