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trini
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u-boot
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ef29884b2708a6cce3b77f4ccaeea193d4e02c22
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cpu
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mpc8xxx
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ddr
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options.c
b4983e1
fsl-ddr: use the 1T timing as default configuration
by Dave Liu
· 16 years ago
7008d26
fsl ddr skip interleaving if not supported.
by Ed Swarthout
· 16 years ago
c9ffd83
Check DDR interleaving mode
by Haiying Wang
· 16 years ago
dfb4910
Pass dimm parameters to populate populate controller options
by Haiying Wang
· 16 years ago
58e5e9a
FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.
by Kumar Gala
· 16 years ago