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gerrit.cesnet.cz / github / trini / u-boot / eb8b3f1edd405504febe6c9797750817b270f543 / board / freescale / p1_p2_rdb / ddr.c
  1. bc2d40c board/p1_p2_rdb:Enable p1_p2_rdb boot from NAND/SD/SPI in SPL by Prabhakar Kushwaha · 11 years ago
  2. 5614e71 Driver/DDR: Moving Freescale DDR driver to a common driver by York Sun · 11 years ago
  3. c63e137 powerpc/mpc8xxx: Add memory reset control by York Sun · 11 years ago
  4. 1a45966 Add GPL-2.0+ SPDX-License-Identifier to source files by Wolfgang Denk · 11 years ago
  5. 67ac13b ppc: Move lbc_clk and cpu to arch_global_data by Simon Glass · 12 years ago
  6. 48f6a5c powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER() by York Sun · 12 years ago
  7. 66c74fc powerpc/85xx: Optimized DDR settings for 800MT/s on P1/P2 RDB by Poonam Aggrwal · 14 years ago
  8. 0c871e95 powerpc/85xx: Use DDR for RAMBOOT instead of L2 SRAM on p1_p2_rdb by Priyanka Jain · 14 years ago
  9. f0f8994 powerpc/85xx: Declare fsl_ddr_set_memctl_regs in <asm/fsl_ddr_sdram.h> by Kumar Gala · 14 years ago
  10. 5cfbc45 powerpc/85xx: Remove DATARATE_*_MHZ defines in static ddr init by Kumar Gala · 14 years ago
  11. 38dba0c mpc85xx boards: initdram() cleanup/bugfix by Becky Bruce · 14 years ago
  12. d3bee08 85xx/p1_p2_rdb: Modify the CLK_CTRL value for DDR at 667MHz by Poonam Aggrwal · 14 years ago
  13. 273a28a 85xx/p1_p2_rdb: Fixing DDR configuration for 800MHz data rate by Poonam Aggrwal · 15 years ago
  14. 924024c 85xx/p1_p2rdb: Fix crash while configuring 32 bit DDR i/f for P1020RDB. by Poonam Aggrwal · 15 years ago
  15. 82b7725 ppc/85xx: 32bit DDR changes for P1020/P1011 by Poonam Aggrwal · 15 years ago
  16. 2abbd31 ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist by Kumar Gala · 15 years ago
  17. 728ece3 85xx: Add support for P2020RDB board by Poonam Aggrwal · 15 years ago