1. a3ab2ae MIPS: sync processor and register definitions with linux-4.4 by Daniel Schwierzeck · 9 years ago
  2. 73a4152 mips: Use unsigned int when reading c0 registers by Chris Packham · 9 years ago
  3. fa476f7 mips32: detect L1 cache sizes if they're not defined by Paul Burton · 11 years ago
  4. 819833a Move architecture-specific includes to arch/$ARCH/include/asm by Peter Tyser · 15 years ago[Renamed from include/asm-mips/mipsregs.h]
  5. e2ad842 [MIPS] <asm/mipsregs.h>: Update coprocessor register access macros by Shinya Kuribayashi · 17 years ago
  6. 1a3adac [MIPS] <asm/mipsregs.h>: Update register / bit field definitions by Shinya Kuribayashi · 17 years ago
  7. bf462ae [MIPS] <asm/mipsregs.h>: CodinygStyle cleanups by Shinya Kuribayashi · 17 years ago
  8. 53677ef Big white-space cleanup. by Wolfgang Denk · 17 years ago
  9. 5da627a * Patch by Steven Scholz, 10 Oct 2003 - Add support for Altera FPGA ACEX1K by wdenk · 21 years ago LABEL_2003_10_09_2320
  10. 8bde7f7 * Code cleanup: by wdenk · 21 years ago LABEL_2003_06_27_2340
  11. 6069ff2 * Add support for 16 MB flash configuration of TRAB board by wdenk · 22 years ago LABEL_2003_02_28_0150