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gerrit.cesnet.cz / github / trini / u-boot / c360ceac0286159f94d9d1a9496fc9858c8d9bec / cpu / mpc8xxx / ddr / ctrl_regs.c
  1. c360cea fsl-ddr: add the DDR3 SPD infrastructure by Dave Liu · 16 years ago
  2. 6a81978 fsl-ddr: Fix two bugs in the ddr infrastructure by Dave Liu · 16 years ago
  3. 22cca7e fsl-ddr: make the self refresh idle threshold configurable by Dave Liu · 16 years ago
  4. 22ff3d0 fsl-ddr: clean up the ddr code for DDR3 controller by Dave Liu · 16 years ago
  5. 80ee3ce fsl-ddr: update the bit mask for DDR3 controller by Dave Liu · 16 years ago
  6. 1f293b4 Add debug information for DDR controller registers by Haiying Wang · 16 years ago
  7. dbbbb3a Make DDR interleaving mode work correctly by Haiying Wang · 16 years ago
  8. 302e52e Fix compiler warning in mpc8xxx ddr code by Kumar Gala · 16 years ago
  9. 58e5e9a FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · 16 years ago