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trini
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u-boot
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c360ceac0286159f94d9d1a9496fc9858c8d9bec
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cpu
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mpc8xxx
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ddr
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ctrl_regs.c
c360cea
fsl-ddr: add the DDR3 SPD infrastructure
by Dave Liu
· 16 years ago
6a81978
fsl-ddr: Fix two bugs in the ddr infrastructure
by Dave Liu
· 16 years ago
22cca7e
fsl-ddr: make the self refresh idle threshold configurable
by Dave Liu
· 16 years ago
22ff3d0
fsl-ddr: clean up the ddr code for DDR3 controller
by Dave Liu
· 16 years ago
80ee3ce
fsl-ddr: update the bit mask for DDR3 controller
by Dave Liu
· 16 years ago
1f293b4
Add debug information for DDR controller registers
by Haiying Wang
· 16 years ago
dbbbb3a
Make DDR interleaving mode work correctly
by Haiying Wang
· 16 years ago
302e52e
Fix compiler warning in mpc8xxx ddr code
by Kumar Gala
· 16 years ago
58e5e9a
FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.
by Kumar Gala
· 16 years ago