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gerrit.cesnet.cz / github / trini / u-boot / a4c66509f1b95884e5753d5a30cf2cf884adb821 / arch / powerpc / cpu / mpc8xxx / ddr / main.c
  1. a4c6650 powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving by York Sun · 12 years ago
  2. 98de369 powerpc/ddr: fix fsl_ddr_get_dimm_params compile error by Shaohui Xie · 12 years ago
  3. 6f5e1dc powerpc/8xxx: Add support for interactive DDR programming interface by York Sun · 13 years ago
  4. 639f330 powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slots by York Sun · 13 years ago
  5. f2d264b powerpc/mpc8xxx: Adding fallback to raw timing on supported boards by York Sun · 13 years ago
  6. 1b3e3c4 powerpc/mpc8xxx: Enable calculation for fixed DDR chips by York Sun · 13 years ago
  7. 51d498f powerpc/mpc8xxx: Add 16-bit support for DDR3 by York Sun · 13 years ago
  8. c39f44d powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from board by Kumar Gala · 14 years ago
  9. fc0c2b6 8xxx/ddr: add support to only compute the ddr sdram size by Haiying Wang · 14 years ago
  10. 7ea3871 MPC8xxx DDR: align informational prints by Becky Bruce · 14 years ago
  11. 076bff8 powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4 by york · 14 years ago
  12. a47a12b Move arch/ppc to arch/powerpc by Stefan Roese · 15 years ago[Renamed from arch/ppc/cpu/mpc8xxx/ddr/main.c]
  13. 8d1f268 ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU by Peter Tyser · 15 years ago[Renamed from cpu/mpc8xxx/ddr/main.c]
  14. d9c147f 85xx, 86xx: Add common board_add_ram_info() by Peter Tyser · 15 years ago
  15. e7563af fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT by Kumar Gala · 15 years ago
  16. edf0e25 fsl-ddr: Allow system to boot if we have more than 4G of memory by Kumar Gala · 16 years ago
  17. 7008d26 fsl ddr skip interleaving if not supported. by Ed Swarthout · 16 years ago
  18. c9ffd83 Check DDR interleaving mode by Haiying Wang · 16 years ago
  19. dfb4910 Pass dimm parameters to populate populate controller options by Haiying Wang · 16 years ago
  20. dbbbb3a Make DDR interleaving mode work correctly by Haiying Wang · 16 years ago
  21. f12e454 Coding style cleanup, update CHANGELOG by Wolfgang Denk · 16 years ago
  22. 58e5e9a FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · 16 years ago