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gerrit.cesnet.cz / github / trini / u-boot / 8b576fa2c43a3a9e775452c2d4ae2766f6d089bf / cpu / mpc8xxx / ddr / main.c
  1. d9c147f 85xx, 86xx: Add common board_add_ram_info() by Peter Tyser · 15 years ago
  2. e7563af fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT by Kumar Gala · 15 years ago
  3. edf0e25 fsl-ddr: Allow system to boot if we have more than 4G of memory by Kumar Gala · 16 years ago
  4. 7008d26 fsl ddr skip interleaving if not supported. by Ed Swarthout · 16 years ago
  5. c9ffd83 Check DDR interleaving mode by Haiying Wang · 16 years ago
  6. dfb4910 Pass dimm parameters to populate populate controller options by Haiying Wang · 16 years ago
  7. dbbbb3a Make DDR interleaving mode work correctly by Haiying Wang · 16 years ago
  8. f12e454 Coding style cleanup, update CHANGELOG by Wolfgang Denk · 16 years ago
  9. 58e5e9a FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · 16 years ago