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gerrit.cesnet.cz / github / trini / u-boot / 8b576fa2c43a3a9e775452c2d4ae2766f6d089bf / board / freescale / mpc8610hpcd / ddr.c
  1. b4983e1 fsl-ddr: use the 1T timing as default configuration by Dave Liu · 16 years ago
  2. dfb4910 Pass dimm parameters to populate populate controller options by Haiying Wang · 16 years ago
  3. 39aa1a7 FSL DDR: Convert MPC8610HPCD to new DDR code. by Jon Loeliger · 16 years ago