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gerrit.cesnet.cz / github / trini / u-boot / 810cb19003ffe0115d10700fc512a2a743916f20 / arch / powerpc / cpu / mpc8xxx / ddr / options.c
  1. e1fd16b mpc85xx: Enable unique mode registers and dynamic ODT for DDR3 by York Sun · 14 years ago
  2. 47df8f0 mpc8xxx: Enable ECC on/off control in hwconfig by York Sun · 14 years ago
  3. dd50af2 powerpc/8xxx: Add hwconfig APIs to address early parsing used by DDR init by Kumar Gala · 14 years ago
  4. 3dbd5d7 powerpc/8xxx: Move fsl_is_spd() into generic 8xxx ddr code by Kumar Gala · 14 years ago
  5. 5fb8a8a powerpc/8xxx: Improvement to DDR parameters by york · 14 years ago
  6. 7fd101c powerpc/8xxx: Enabled address hashing for 85xx by york · 14 years ago
  7. 5800e7a powerpc/8xxx: Enable quad-rank DIMMs. by york · 14 years ago
  8. 076bff8 powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4 by york · 14 years ago
  9. 79e4e64 powerpc/8xxx: Enabled hwconfig for memory interleaving by Kumar Gala · 14 years ago
  10. a47a12b Move arch/ppc to arch/powerpc by Stefan Roese · 15 years ago[Renamed from arch/ppc/cpu/mpc8xxx/ddr/options.c]
  11. 8d1f268 ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU by Peter Tyser · 15 years ago[Renamed from cpu/mpc8xxx/ddr/options.c]
  12. 22c9de0 fsl-ddr: change the default burst mode for DDR3 by Dave Liu · 15 years ago
  13. bdc9f7b fsl-ddr: add the override for write leveling by Dave Liu · 15 years ago
  14. 3ad95de fsl-ddr: Fix the chip-select interleaving issue by Dave Liu · 15 years ago
  15. c360cea fsl-ddr: add the DDR3 SPD infrastructure by Dave Liu · 16 years ago
  16. 1542fbd fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controller by Kumar Gala · 16 years ago
  17. b4983e1 fsl-ddr: use the 1T timing as default configuration by Dave Liu · 16 years ago
  18. 7008d26 fsl ddr skip interleaving if not supported. by Ed Swarthout · 16 years ago
  19. c9ffd83 Check DDR interleaving mode by Haiying Wang · 16 years ago
  20. dfb4910 Pass dimm parameters to populate populate controller options by Haiying Wang · 16 years ago
  21. 58e5e9a FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · 16 years ago