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gerrit.cesnet.cz / github / trini / u-boot / 810cb19003ffe0115d10700fc512a2a743916f20 / arch / powerpc / cpu / mpc8xxx / ddr / main.c
  1. c39f44d powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from board by Kumar Gala · 14 years ago
  2. fc0c2b6 8xxx/ddr: add support to only compute the ddr sdram size by Haiying Wang · 14 years ago
  3. 7ea3871 MPC8xxx DDR: align informational prints by Becky Bruce · 14 years ago
  4. 076bff8 powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4 by york · 14 years ago
  5. a47a12b Move arch/ppc to arch/powerpc by Stefan Roese · 15 years ago[Renamed from arch/ppc/cpu/mpc8xxx/ddr/main.c]
  6. 8d1f268 ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU by Peter Tyser · 15 years ago[Renamed from cpu/mpc8xxx/ddr/main.c]
  7. d9c147f 85xx, 86xx: Add common board_add_ram_info() by Peter Tyser · 15 years ago
  8. e7563af fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT by Kumar Gala · 15 years ago
  9. edf0e25 fsl-ddr: Allow system to boot if we have more than 4G of memory by Kumar Gala · 16 years ago
  10. 7008d26 fsl ddr skip interleaving if not supported. by Ed Swarthout · 16 years ago
  11. c9ffd83 Check DDR interleaving mode by Haiying Wang · 16 years ago
  12. dfb4910 Pass dimm parameters to populate populate controller options by Haiying Wang · 16 years ago
  13. dbbbb3a Make DDR interleaving mode work correctly by Haiying Wang · 16 years ago
  14. f12e454 Coding style cleanup, update CHANGELOG by Wolfgang Denk · 16 years ago
  15. 58e5e9a FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · 16 years ago