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80ee3ce6d7fe9441b4352d7cfaf6afc2507b1106
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cpu
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mpc8xxx
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ddr
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ctrl_regs.c
80ee3ce
fsl-ddr: update the bit mask for DDR3 controller
by Dave Liu
· 16 years ago
1f293b4
Add debug information for DDR controller registers
by Haiying Wang
· 16 years ago
dbbbb3a
Make DDR interleaving mode work correctly
by Haiying Wang
· 16 years ago
302e52e
Fix compiler warning in mpc8xxx ddr code
by Kumar Gala
· 16 years ago
58e5e9a
FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.
by Kumar Gala
· 16 years ago