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gerrit.cesnet.cz / github / trini / u-boot / 3fee334c85fd16904f8d23487247508cceab0228 / board / freescale / p1_p2_rdb / ddr.c
  1. 38dba0c mpc85xx boards: initdram() cleanup/bugfix by Becky Bruce · 14 years ago
  2. d3bee08 85xx/p1_p2_rdb: Modify the CLK_CTRL value for DDR at 667MHz by Poonam Aggrwal · 14 years ago
  3. 273a28a 85xx/p1_p2_rdb: Fixing DDR configuration for 800MHz data rate by Poonam Aggrwal · 15 years ago
  4. 924024c 85xx/p1_p2rdb: Fix crash while configuring 32 bit DDR i/f for P1020RDB. by Poonam Aggrwal · 15 years ago
  5. 82b7725 ppc/85xx: 32bit DDR changes for P1020/P1011 by Poonam Aggrwal · 15 years ago
  6. 2abbd31 ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist by Kumar Gala · 15 years ago
  7. 728ece3 85xx: Add support for P2020RDB board by Poonam Aggrwal · 15 years ago