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gerrit.cesnet.cz / github / trini / u-boot / 1b8ad819cead7020d35f6251ef0cf3f393c61e51 / drivers / clk / sifive
  1. 65e25be dm: Rename DM_GET_DRIVER() to DM_DRIVER_GET() by Simon Glass · 4 years ago
  2. 41575d8 dm: treewide: Rename auto_alloc_size members to be shorter by Simon Glass · 4 years ago
  3. 0f0f4e5 clk: sifive: Include device_compat.h by Sean Anderson · 4 years, 2 months ago
  4. d04a464 sifive: reset: add DM based reset driver for SiFive SoC's by Sagar Shrikant Kadam · 4 years, 4 months ago
  5. d2e4398 fu540: prci: use common reset indexes defined in binding header by Sagar Shrikant Kadam · 4 years, 4 months ago
  6. 1ba43d2 clk: sifive: fu540-prci: Release ethernet clock reset by Pragnesh Patel · 4 years, 6 months ago
  7. 378c709 clk: sifive: fu540-prci: Add ddr clock initialization by Pragnesh Patel · 4 years, 6 months ago
  8. 79e49b0 clk: sifive: fu540-prci: Add clock enable and disable ops by Pragnesh Patel · 4 years, 6 months ago
  9. c05ed00 common: Drop linux/delay.h from common header by Simon Glass · 4 years, 7 months ago
  10. 61b29b8 dm: core: Require users of devres to include the header by Simon Glass · 4 years, 10 months ago
  11. 8633ede clk: sifive: Drop GEMGXL clock driver by Anup Patel · 5 years ago
  12. ed0ef37 clk: sifive: Sync-up main driver with upstream Linux by Anup Patel · 5 years ago
  13. 66591a7 clk: sifive: Sync-up DT bindings header with upstream Linux by Anup Patel · 5 years ago
  14. c236802 clk: sifive: Sync-up WRPLL library with upstream Linux by Anup Patel · 5 years ago
  15. d04c79d clk: sifive: Factor-out PLL library as separate module by Anup Patel · 5 years ago
  16. 49191d2 clk: sifive: Add clock driver for GEMGXL MGMT by Bin Meng · 6 years ago
  17. db2f696 clk: sifive: fu540-prci: Change include order by Jagan Teki · 6 years ago
  18. c40b6df clk: Add SiFive FU540 PRCI clock driver by Anup Patel · 6 years ago