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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * m8xx.c
26 *
27 * CPU specific code
28 *
29 * written or collected and sometimes rewritten by
30 * Magnus Damm <damm@bitsmart.com>
31 *
32 * minor modifications by
33 * Wolfgang Denk <wd@denx.de>
34 */
35
36#include <common.h>
37#include <watchdog.h>
38#include <command.h>
39#include <mpc8xx.h>
40#include <asm/cache.h>
41
42static char *cpu_warning = "\n " \
43 "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
44
wdenk2535d602003-07-17 23:16:40 +000045#if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \
wdenkc6097192002-11-03 00:24:07 +000046 !defined(CONFIG_MPC862))
wdenk2535d602003-07-17 23:16:40 +000047
wdenkc6097192002-11-03 00:24:07 +000048static int check_CPU (long clock, uint pvr, uint immr)
49{
wdenk180d3f72004-01-04 16:28:35 +000050 char *id_str =
51# if defined(CONFIG_MPC855)
52 "PC855";
53# elif defined(CONFIG_MPC860P)
54 "PC860P";
55# else
56 NULL;
57# endif
wdenkc6097192002-11-03 00:24:07 +000058 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
59 uint k, m;
60 char buf[32];
61 char pre = 'X';
62 char *mid = "xx";
63 char *suf;
64
65 /* the highest 16 bits should be 0x0050 for a 860 */
66
67 if ((pvr >> 16) != 0x0050)
68 return -1;
69
70 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
71 m = 0;
72
wdenk180d3f72004-01-04 16:28:35 +000073 /*
74 * Some boards use sockets so different CPUs can be used.
75 * We have to check chip version in run time.
76 */
wdenkc6097192002-11-03 00:24:07 +000077 switch (k) {
wdenk180d3f72004-01-04 16:28:35 +000078 case 0x00020001: pre = 'P'; suf = ""; break;
wdenkc6097192002-11-03 00:24:07 +000079 case 0x00030001: suf = ""; break;
80 case 0x00120003: suf = "A"; break;
81 case 0x00130003: suf = "A3"; break;
82
83 case 0x00200004: suf = "B"; break;
84
85 case 0x00300004: suf = "C"; break;
wdenk2535d602003-07-17 23:16:40 +000086 case 0x00310004: suf = "C1"; m = 1; break;
wdenkc6097192002-11-03 00:24:07 +000087
88 case 0x00200064: mid = "SR"; suf = "B"; break;
89 case 0x00300065: mid = "SR"; suf = "C"; break;
90 case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break;
91 case 0x05010000: suf = "D3"; m = 1; break;
92 case 0x05020000: suf = "D4"; m = 1; break;
wdenkc6097192002-11-03 00:24:07 +000093 /* this value is not documented anywhere */
94 case 0x40000000: pre = 'P'; suf = "D"; m = 1; break;
wdenk180d3f72004-01-04 16:28:35 +000095 /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
96 case 0x08000003: pre = 'M'; suf = ""; m = 1;
97 if (id_str == NULL)
98 id_str =
99# if defined(CONFIG_MPC852T)
100 "PC852T";
101# elif defined(CONFIG_MPC859T)
102 "PC859T";
103# elif defined(CONFIG_MPC859DSL)
104 "PC859DSL";
105# elif defined(CONFIG_MPC866T)
106 "PC866T";
107# else
108 "PC866x"; /* Unknown chip from MPC866 family */
109# endif
110 break;
111 case 0x09000000: pre = 'M'; mid = suf = ""; m = 1;
112 if (id_str == NULL)
113 id_str = "PC885"; /* 870/875/880/885 */
114 break;
wdenkc6097192002-11-03 00:24:07 +0000115
116 default: suf = NULL; break;
117 }
118
wdenk180d3f72004-01-04 16:28:35 +0000119 if (id_str == NULL)
120 id_str = "PC86x"; /* Unknown 86x chip */
wdenkc6097192002-11-03 00:24:07 +0000121 if (suf)
wdenk180d3f72004-01-04 16:28:35 +0000122 printf ("%c%s%sZPnn%s", pre, id_str, mid, suf);
wdenkc6097192002-11-03 00:24:07 +0000123 else
wdenk180d3f72004-01-04 16:28:35 +0000124 printf ("unknown M%s (0x%08x)", id_str, k);
wdenkc6097192002-11-03 00:24:07 +0000125
wdenkc6097192002-11-03 00:24:07 +0000126
wdenk66ca92a2004-09-28 17:59:53 +0000127#if defined(CFG_8xx_CPUCLK_MIN) && defined(CFG_8xx_CPUCLK_MAX)
wdenk75d1ea72004-01-31 20:06:54 +0000128 printf (" at %s MHz [%d.%d...%d.%d MHz]\n ",
129 strmhz (buf, clock),
wdenk66ca92a2004-09-28 17:59:53 +0000130 CFG_8xx_CPUCLK_MIN / 1000000,
131 ((CFG_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000,
132 CFG_8xx_CPUCLK_MAX / 1000000,
133 ((CFG_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000
wdenk75d1ea72004-01-31 20:06:54 +0000134 );
135#else
136 printf (" at %s MHz: ", strmhz (buf, clock));
137#endif
138 printf ("%u kB I-Cache %u kB D-Cache",
139 checkicache () >> 10,
140 checkdcache () >> 10
141 );
wdenkc6097192002-11-03 00:24:07 +0000142
wdenk66ca92a2004-09-28 17:59:53 +0000143 /* do we have a FEC (860T/P or 852/859/866/885)? */
wdenkc6097192002-11-03 00:24:07 +0000144
145 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
146 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
147 printf (" FEC present");
148 }
149
150 if (!m) {
151 puts (cpu_warning);
152 }
153
154 putc ('\n');
155
wdenk2535d602003-07-17 23:16:40 +0000156#ifdef DEBUG
wdenk42d1f032003-10-15 23:53:47 +0000157 if(clock != measure_gclk()) {
158 printf ("clock %ldHz != %dHz\n", clock, measure_gclk());
159 }
wdenk2535d602003-07-17 23:16:40 +0000160#endif
161
wdenkc6097192002-11-03 00:24:07 +0000162 return 0;
163}
164
165#elif defined(CONFIG_MPC862)
166
167static int check_CPU (long clock, uint pvr, uint immr)
168{
169 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
170 uint k, m;
171 char buf[32];
172 char pre = 'X';
173 char *mid = "xx";
174 char *suf;
175
176 /* the highest 16 bits should be 0x0050 for a 8xx */
177
178 if ((pvr >> 16) != 0x0050)
179 return -1;
180
181 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
182 m = 0;
183
184 switch (k) {
185
186 /* this value is not documented anywhere */
187 case 0x06000000: mid = "P"; suf = "0"; break;
188 case 0x06010001: mid = "P"; suf = "A"; m = 1; break;
189 case 0x07000003: mid = "P"; suf = "B"; m = 1; break;
190 default: suf = NULL; break;
191 }
192
193 if (suf)
194 printf ("%cPC862%sZPnn%s", pre, mid, suf);
195 else
196 printf ("unknown MPC862 (0x%08x)", k);
197
198 printf (" at %s MHz:", strmhz (buf, clock));
199
200 printf (" %u kB I-Cache", checkicache () >> 10);
201 printf (" %u kB D-Cache", checkdcache () >> 10);
202
203 /* lets check and see if we're running on a 862T (or P?) */
204
205 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
206 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
207 printf (" FEC present");
208 }
209
210 if (!m) {
211 puts (cpu_warning);
212 }
213
214 putc ('\n');
215
216 return 0;
217}
218
219#elif defined(CONFIG_MPC823)
220
221static int check_CPU (long clock, uint pvr, uint immr)
222{
223 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
224 uint k, m;
225 char buf[32];
226 char *suf;
227
228 /* the highest 16 bits should be 0x0050 for a 8xx */
229
230 if ((pvr >> 16) != 0x0050)
231 return -1;
232
233 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
234 m = 0;
235
236 switch (k) {
237 /* MPC823 */
238 case 0x20000000: suf = "0"; break;
239 case 0x20010000: suf = "0.1"; break;
240 case 0x20020000: suf = "Z2/3"; break;
241 case 0x20020001: suf = "Z3"; break;
242 case 0x21000000: suf = "A"; break;
243 case 0x21010000: suf = "B"; m = 1; break;
244 case 0x21010001: suf = "B2"; m = 1; break;
245 /* MPC823E */
246 case 0x24010000: suf = NULL;
247 puts ("PPC823EZTnnB2");
248 m = 1;
249 break;
250 default:
251 suf = NULL;
252 printf ("unknown MPC823 (0x%08x)", k);
253 break;
254 }
255 if (suf)
256 printf ("PPC823ZTnn%s", suf);
257
258 printf (" at %s MHz:", strmhz (buf, clock));
259
260 printf (" %u kB I-Cache", checkicache () >> 10);
261 printf (" %u kB D-Cache", checkdcache () >> 10);
262
263 /* lets check and see if we're running on a 860T (or P?) */
264
265 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
266 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
267 puts (" FEC present");
268 }
269
270 if (!m) {
271 puts (cpu_warning);
272 }
273
274 putc ('\n');
275
276 return 0;
277}
278
279#elif defined(CONFIG_MPC850)
280
281static int check_CPU (long clock, uint pvr, uint immr)
282{
283 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
284 uint k, m;
285 char buf[32];
286
287 /* the highest 16 bits should be 0x0050 for a 8xx */
288
289 if ((pvr >> 16) != 0x0050)
290 return -1;
291
292 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
293 m = 0;
294
295 switch (k) {
296 case 0x20020001:
297 printf ("XPC850xxZT");
298 break;
299 case 0x21000065:
300 printf ("XPC850xxZTA");
301 break;
302 case 0x21010067:
303 printf ("XPC850xxZTB");
304 m = 1;
305 break;
306 case 0x21020068:
307 printf ("XPC850xxZTC");
308 m = 1;
309 break;
310 default:
311 printf ("unknown MPC850 (0x%08x)", k);
312 }
313 printf (" at %s MHz:", strmhz (buf, clock));
314
315 printf (" %u kB I-Cache", checkicache () >> 10);
316 printf (" %u kB D-Cache", checkdcache () >> 10);
317
318 /* lets check and see if we're running on a 850T (or P?) */
319
320 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
321 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
322 printf (" FEC present");
323 }
324
325 if (!m) {
326 puts (cpu_warning);
327 }
328
329 putc ('\n');
330
331 return 0;
332}
333#else
334#error CPU undefined
335#endif
336/* ------------------------------------------------------------------------- */
337
338int checkcpu (void)
339{
340 DECLARE_GLOBAL_DATA_PTR;
341
342 ulong clock = gd->cpu_clk;
343 uint immr = get_immr (0); /* Return full IMMR contents */
344 uint pvr = get_pvr ();
345
346 puts ("CPU: ");
347
348 /* 850 has PARTNUM 20 */
349 /* 801 has PARTNUM 10 */
350 return check_CPU (clock, pvr, immr);
351}
352
353/* ------------------------------------------------------------------------- */
354/* L1 i-cache */
355/* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
356/* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB) */
357
358int checkicache (void)
359{
360 volatile immap_t *immap = (immap_t *) CFG_IMMR;
361 volatile memctl8xx_t *memctl = &immap->im_memctl;
362 u32 cacheon = rd_ic_cst () & IDC_ENABLED;
363
wdenk2535d602003-07-17 23:16:40 +0000364#ifdef CONFIG_IP86x
wdenkc6097192002-11-03 00:24:07 +0000365 u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
366#else
367 u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
368#endif
369 u32 m;
370 u32 lines = -1;
371
372 wr_ic_cst (IDC_UNALL);
373 wr_ic_cst (IDC_INVALL);
374 wr_ic_cst (IDC_DISABLE);
375 __asm__ volatile ("isync");
376
377 while (!((m = rd_ic_cst ()) & IDC_CERR2)) {
378 wr_ic_adr (k);
379 wr_ic_cst (IDC_LDLCK);
380 __asm__ volatile ("isync");
381
382 lines++;
383 k += 0x10; /* the number of bytes in a cacheline */
384 }
385
386 wr_ic_cst (IDC_UNALL);
387 wr_ic_cst (IDC_INVALL);
388
389 if (cacheon)
390 wr_ic_cst (IDC_ENABLE);
391 else
392 wr_ic_cst (IDC_DISABLE);
393
394 __asm__ volatile ("isync");
395
396 return lines << 4;
397};
398
399/* ------------------------------------------------------------------------- */
400/* L1 d-cache */
401/* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
402/* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB) */
403/* call with cache disabled */
404
405int checkdcache (void)
406{
407 volatile immap_t *immap = (immap_t *) CFG_IMMR;
408 volatile memctl8xx_t *memctl = &immap->im_memctl;
409 u32 cacheon = rd_dc_cst () & IDC_ENABLED;
410
wdenk2535d602003-07-17 23:16:40 +0000411#ifdef CONFIG_IP86x
wdenkc6097192002-11-03 00:24:07 +0000412 u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
413#else
414 u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
415#endif
416 u32 m;
417 u32 lines = -1;
418
419 wr_dc_cst (IDC_UNALL);
420 wr_dc_cst (IDC_INVALL);
421 wr_dc_cst (IDC_DISABLE);
422
423 while (!((m = rd_dc_cst ()) & IDC_CERR2)) {
424 wr_dc_adr (k);
425 wr_dc_cst (IDC_LDLCK);
426 lines++;
427 k += 0x10; /* the number of bytes in a cacheline */
428 }
429
430 wr_dc_cst (IDC_UNALL);
431 wr_dc_cst (IDC_INVALL);
432
433 if (cacheon)
434 wr_dc_cst (IDC_ENABLE);
435 else
436 wr_dc_cst (IDC_DISABLE);
437
438 return lines << 4;
439};
440
441/* ------------------------------------------------------------------------- */
442
443void upmconfig (uint upm, uint * table, uint size)
444{
445 uint i;
446 uint addr = 0;
447 volatile immap_t *immap = (immap_t *) CFG_IMMR;
448 volatile memctl8xx_t *memctl = &immap->im_memctl;
449
450 for (i = 0; i < size; i++) {
451 memctl->memc_mdr = table[i]; /* (16-15) */
452 memctl->memc_mcr = addr | upm; /* (16-16) */
453 addr++;
454 }
455}
456
457/* ------------------------------------------------------------------------- */
458
wdenk8bde7f72003-06-27 21:31:46 +0000459int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
wdenkc6097192002-11-03 00:24:07 +0000460{
461 ulong msr, addr;
462
463 volatile immap_t *immap = (immap_t *) CFG_IMMR;
464
465 immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */
466
467 /* Interrupts and MMU off */
468 __asm__ volatile ("mtspr 81, 0");
469 __asm__ volatile ("mfmsr %0":"=r" (msr));
470
471 msr &= ~0x1030;
472 __asm__ volatile ("mtmsr %0"::"r" (msr));
473
474 /*
475 * Trying to execute the next instruction at a non-existing address
476 * should cause a machine check, resulting in reset
477 */
478#ifdef CFG_RESET_ADDRESS
479 addr = CFG_RESET_ADDRESS;
480#else
481 /*
482 * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE
483 * - sizeof (ulong) is usually a valid address. Better pick an address
484 * known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
485 * "(ulong)-1" used to be a good choice for many systems...
486 */
487 addr = CFG_MONITOR_BASE - sizeof (ulong);
488#endif
489 ((void (*)(void)) addr) ();
490 return 1;
491}
492
493/* ------------------------------------------------------------------------- */
494
495/*
496 * Get timebase clock frequency (like cpu_clk in Hz)
497 *
wdenk180d3f72004-01-04 16:28:35 +0000498 * See sections 14.2 and 14.6 of the User's Manual
wdenkc6097192002-11-03 00:24:07 +0000499 */
500unsigned long get_tbclk (void)
501{
502 DECLARE_GLOBAL_DATA_PTR;
503
wdenk180d3f72004-01-04 16:28:35 +0000504 uint immr = get_immr (0); /* Return full IMMR contents */
505 volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000);
506 ulong oscclk, factor, pll;
wdenkc6097192002-11-03 00:24:07 +0000507
wdenk180d3f72004-01-04 16:28:35 +0000508 if (immap->im_clkrst.car_sccr & SCCR_TBS) {
wdenkc6097192002-11-03 00:24:07 +0000509 return (gd->cpu_clk / 16);
510 }
511
wdenk180d3f72004-01-04 16:28:35 +0000512 pll = immap->im_clkrst.car_plprcr;
513
514#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
515
516 /*
517 * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
518 * factor is calculated as follows:
519 *
520 * MFN
521 * MFI + -------
522 * MFD + 1
523 * factor = -----------------
524 * (PDF + 1) * 2^S
525 *
526 * For older chips, it's just MF field of PLPRCR plus one.
527 */
wdenkb0aef112004-01-18 18:21:54 +0000528 if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
wdenk180d3f72004-01-04 16:28:35 +0000529 factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
530 (PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
531 } else {
532 factor = PLPRCR_val(MF)+1;
533 }
wdenkc6097192002-11-03 00:24:07 +0000534
535 oscclk = gd->cpu_clk / factor;
536
wdenk180d3f72004-01-04 16:28:35 +0000537 if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) {
wdenkc6097192002-11-03 00:24:07 +0000538 return (oscclk / 4);
539 }
540 return (oscclk / 16);
541}
542
543/* ------------------------------------------------------------------------- */
544
545#if defined(CONFIG_WATCHDOG)
546void watchdog_reset (void)
547{
548 int re_enable = disable_interrupts ();
549
550 reset_8xx_watchdog ((immap_t *) CFG_IMMR);
551 if (re_enable)
552 enable_interrupts ();
553}
554
555void reset_8xx_watchdog (volatile immap_t * immr)
556{
557# if defined(CONFIG_LWMON)
558 /*
559 * The LWMON board uses a MAX6301 Watchdog
560 * with the trigger pin connected to port PA.7
561 *
562 * (The old board version used a MAX706TESA Watchdog, which
563 * had to be handled exactly the same.)
564 */
565# define WATCHDOG_BIT 0x0100
566 immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
567 immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */
568 immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
569
570 immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
wdenk02b11f82004-05-12 22:54:36 +0000571# elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
572 /*
573 * The KUP4 boards uses a TPS3705 Watchdog
574 * with the trigger pin connected to port PA.5
575 */
576# define WATCHDOG_BIT 0x0400
577 immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
578 immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */
579 immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
580
581 immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
wdenkc6097192002-11-03 00:24:07 +0000582# else
583 /*
584 * All other boards use the MPC8xx Internal Watchdog
585 */
586 immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */
587 immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */
588# endif /* CONFIG_LWMON */
589}
590
591#endif /* CONFIG_WATCHDOG */
592
593/* ------------------------------------------------------------------------- */