blob: 43b7f2281440f3f48fb976848bbffa7c5f15b507 [file] [log] [blame]
Simon Glassc3691392014-09-04 16:27:35 -06001#include <dt-bindings/clock/tegra124-car.h>
Simon Glass89460342014-06-11 23:29:52 -06002#include <dt-bindings/gpio/tegra-gpio.h>
Simon Glass754204b2014-12-04 06:36:29 -07003#include <dt-bindings/pinctrl/pinctrl-tegra.h>
Simon Glass89460342014-06-11 23:29:52 -06004#include <dt-bindings/interrupt-controller/arm-gic.h>
Thierry Reding78e9f1c2014-12-09 22:25:10 -07005#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
Simon Glass89460342014-06-11 23:29:52 -06006
Tom Warrena57c5842014-01-24 12:46:17 -07007#include "skeleton.dtsi"
8
9/ {
10 compatible = "nvidia,tegra124";
Thierry Reding12e5f6a2014-12-09 22:25:19 -070011 interrupt-parent = <&gic>;
12
Thierry Reding9c46e6c2014-12-09 22:25:20 -070013 pcie-controller@01003000 {
14 compatible = "nvidia,tegra124-pcie";
15 device_type = "pci";
16 reg = <0x01003000 0x00000800 /* PADS registers */
17 0x01003800 0x00000800 /* AFI registers */
18 0x02000000 0x10000000>; /* configuration space */
19 reg-names = "pads", "afi", "cs";
20 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
21 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
22 interrupt-names = "intr", "msi";
23
24 #interrupt-cells = <1>;
25 interrupt-map-mask = <0 0 0 0>;
26 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
27
28 bus-range = <0x00 0xff>;
29 #address-cells = <3>;
30 #size-cells = <2>;
31
32 ranges = <0x82000000 0 0x01000000 0x01000000 0 0x00001000 /* port 0 configuration space */
33 0x82000000 0 0x01001000 0x01001000 0 0x00001000 /* port 1 configuration space */
34 0x81000000 0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
35 0x82000000 0 0x13000000 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
36 0xc2000000 0 0x20000000 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
37
38 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
39 <&tegra_car TEGRA124_CLK_AFI>,
40 <&tegra_car TEGRA124_CLK_PLL_E>,
41 <&tegra_car TEGRA124_CLK_CML0>;
42 clock-names = "pex", "afi", "pll_e", "cml";
43 resets = <&tegra_car 70>,
44 <&tegra_car 72>,
45 <&tegra_car 74>;
46 reset-names = "pex", "afi", "pcie_x";
47 status = "disabled";
48
49 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
50 phy-names = "pcie";
51
52 pci@1,0 {
53 device_type = "pci";
54 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
55 reg = <0x000800 0 0 0 0>;
56 status = "disabled";
57
58 #address-cells = <3>;
59 #size-cells = <2>;
60 ranges;
61
62 nvidia,num-lanes = <2>;
63 };
64
65 pci@2,0 {
66 device_type = "pci";
67 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
68 reg = <0x001000 0 0 0 0>;
69 status = "disabled";
70
71 #address-cells = <3>;
72 #size-cells = <2>;
73 ranges;
74
75 nvidia,num-lanes = <1>;
76 };
77 };
78
Simon Glassffc78992015-04-14 21:03:30 -060079 host1x@50000000 {
80 compatible = "nvidia,tegra124-host1x", "simple-bus";
81 reg = <0x50000000 0x00034000>;
82 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
83 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
84 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
85 resets = <&tegra_car 28>;
86 reset-names = "host1x";
87
88 #address-cells = <1>;
89 #size-cells = <1>;
90
91 ranges = <0x54000000 0x54000000 0x01000000>;
92
93 dc@54200000 {
94 compatible = "nvidia,tegra124-dc";
95 reg = <0x54200000 0x00040000>;
96 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
97 clocks = <&tegra_car TEGRA124_CLK_DISP1>,
98 <&tegra_car TEGRA124_CLK_PLL_P>;
99 clock-names = "dc", "parent";
100 resets = <&tegra_car 27>;
101 reset-names = "dc";
102
103 nvidia,head = <0>;
104 };
105
106 dc@54240000 {
107 compatible = "nvidia,tegra124-dc";
108 reg = <0x54240000 0x00040000>;
109 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&tegra_car TEGRA124_CLK_DISP2>,
111 <&tegra_car TEGRA124_CLK_PLL_P>;
112 clock-names = "dc", "parent";
113 resets = <&tegra_car 26>;
114 reset-names = "dc";
115
116 nvidia,head = <1>;
117 };
118
119 hdmi@54280000 {
120 compatible = "nvidia,tegra124-hdmi";
121 reg = <0x54280000 0x00040000>;
122 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
123 clocks = <&tegra_car TEGRA124_CLK_HDMI>,
124 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
125 clock-names = "hdmi", "parent";
126 resets = <&tegra_car 51>;
127 reset-names = "hdmi";
128 status = "disabled";
129 };
130
131 sor@54540000 {
132 compatible = "nvidia,tegra124-sor";
133 reg = <0x54540000 0x00040000>;
134 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
135 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
136 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
137 <&tegra_car TEGRA124_CLK_PLL_DP>,
138 <&tegra_car TEGRA124_CLK_CLK_M>;
139 clock-names = "sor", "parent", "dp", "safe";
140 resets = <&tegra_car 182>;
141 reset-names = "sor";
142 status = "disabled";
143 };
144
145 dpaux: dpaux@545c0000 {
146 compatible = "nvidia,tegra124-dpaux";
147 reg = <0x545c0000 0x00040000>;
148 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
149 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
150 <&tegra_car TEGRA124_CLK_PLL_DP>;
151 clock-names = "dpaux", "parent";
152 resets = <&tegra_car 181>;
153 reset-names = "dpaux";
154 status = "disabled";
155 };
156 };
157
Thierry Reding12e5f6a2014-12-09 22:25:19 -0700158 gic: interrupt-controller@50041000 {
159 compatible = "arm,cortex-a15-gic";
160 #interrupt-cells = <3>;
161 interrupt-controller;
162 reg = <0x50041000 0x1000>,
163 <0x50042000 0x2000>,
164 <0x50044000 0x2000>,
165 <0x50046000 0x2000>;
166 interrupts = <GIC_PPI 9
167 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
168 };
Tom Warrena57c5842014-01-24 12:46:17 -0700169
170 tegra_car: clock@60006000 {
171 compatible = "nvidia,tegra124-car";
172 reg = <0x60006000 0x1000>;
173 #clock-cells = <1>;
174 };
175
176 apbdma: dma@60020000 {
177 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
178 reg = <0x60020000 0x1400>;
179 interrupts = <0 104 0x04
180 0 105 0x04
181 0 106 0x04
182 0 107 0x04
183 0 108 0x04
184 0 109 0x04
185 0 110 0x04
186 0 111 0x04
187 0 112 0x04
188 0 113 0x04
189 0 114 0x04
190 0 115 0x04
191 0 116 0x04
192 0 117 0x04
193 0 118 0x04
194 0 119 0x04
195 0 128 0x04
196 0 129 0x04
197 0 130 0x04
198 0 131 0x04
199 0 132 0x04
200 0 133 0x04
201 0 134 0x04
202 0 135 0x04
203 0 136 0x04
204 0 137 0x04
205 0 138 0x04
206 0 139 0x04
207 0 140 0x04
208 0 141 0x04
209 0 142 0x04
210 0 143 0x04>;
211 };
212
213 gpio: gpio@6000d000 {
214 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
215 reg = <0x6000d000 0x1000>;
Simon Glass89460342014-06-11 23:29:52 -0600216 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
Tom Warrena57c5842014-01-24 12:46:17 -0700224 #gpio-cells = <2>;
225 gpio-controller;
226 #interrupt-cells = <2>;
227 interrupt-controller;
228 };
229
230 i2c@7000c000 {
231 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
232 reg = <0x7000c000 0x100>;
233 interrupts = <0 38 0x04>;
234 #address-cells = <1>;
235 #size-cells = <0>;
236 clocks = <&tegra_car 12>;
237 status = "disabled";
238 };
239
240 i2c@7000c400 {
241 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
242 reg = <0x7000c400 0x100>;
243 interrupts = <0 84 0x04>;
244 #address-cells = <1>;
245 #size-cells = <0>;
246 clocks = <&tegra_car 54>;
247 status = "disabled";
248 };
249
250 i2c@7000c500 {
251 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
252 reg = <0x7000c500 0x100>;
253 interrupts = <0 92 0x04>;
254 #address-cells = <1>;
255 #size-cells = <0>;
256 clocks = <&tegra_car 67>;
257 status = "disabled";
258 };
259
260 i2c@7000c700 {
261 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
262 reg = <0x7000c700 0x100>;
263 interrupts = <0 120 0x04>;
264 #address-cells = <1>;
265 #size-cells = <0>;
266 clocks = <&tegra_car 103>;
267 status = "disabled";
268 };
269
270 i2c@7000d000 {
271 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
272 reg = <0x7000d000 0x100>;
273 interrupts = <0 53 0x04>;
274 #address-cells = <1>;
275 #size-cells = <0>;
276 clocks = <&tegra_car 47>;
277 status = "disabled";
278 };
279
280 i2c@7000d100 {
281 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
282 reg = <0x7000d100 0x100>;
283 interrupts = <0 53 0x04>;
284 #address-cells = <1>;
285 #size-cells = <0>;
286 clocks = <&tegra_car 47>;
287 status = "disabled";
288 };
289
Simon Glassc3691392014-09-04 16:27:35 -0600290 uarta: serial@70006000 {
291 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
292 reg = <0x70006000 0x40>;
293 reg-shift = <2>;
294 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
296 resets = <&tegra_car 6>;
297 reset-names = "serial";
298 dmas = <&apbdma 8>, <&apbdma 8>;
299 dma-names = "rx", "tx";
300 status = "disabled";
301 };
302
303 uartb: serial@70006040 {
304 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
305 reg = <0x70006040 0x40>;
306 reg-shift = <2>;
307 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
309 resets = <&tegra_car 7>;
310 reset-names = "serial";
311 dmas = <&apbdma 9>, <&apbdma 9>;
312 dma-names = "rx", "tx";
313 status = "disabled";
314 };
315
316 uartc: serial@70006200 {
317 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
318 reg = <0x70006200 0x40>;
319 reg-shift = <2>;
320 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
322 resets = <&tegra_car 55>;
323 reset-names = "serial";
324 dmas = <&apbdma 10>, <&apbdma 10>;
325 dma-names = "rx", "tx";
326 status = "disabled";
327 };
328
329 uartd: serial@70006300 {
330 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
331 reg = <0x70006300 0x40>;
332 reg-shift = <2>;
333 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
335 resets = <&tegra_car 65>;
336 reset-names = "serial";
337 dmas = <&apbdma 19>, <&apbdma 19>;
338 dma-names = "rx", "tx";
339 status = "disabled";
340 };
341
342 uarte: serial@70006400 {
343 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
344 reg = <0x70006400 0x40>;
345 reg-shift = <2>;
346 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&tegra_car TEGRA124_CLK_UARTE>;
348 resets = <&tegra_car 66>;
349 reset-names = "serial";
350 dmas = <&apbdma 20>, <&apbdma 20>;
351 dma-names = "rx", "tx";
352 status = "disabled";
353 };
354
Simon Glass754204b2014-12-04 06:36:29 -0700355 pwm: pwm@7000a000 {
356 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
357 reg = <0x7000a000 0x100>;
358 #pwm-cells = <2>;
359 clocks = <&tegra_car TEGRA124_CLK_PWM>;
360 resets = <&tegra_car 17>;
361 reset-names = "pwm";
362 status = "disabled";
363 };
364
Tom Warrena57c5842014-01-24 12:46:17 -0700365 spi@7000d400 {
366 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
367 reg = <0x7000d400 0x200>;
368 interrupts = <0 59 0x04>;
369 nvidia,dma-request-selector = <&apbdma 15>;
370 #address-cells = <1>;
371 #size-cells = <0>;
372 status = "disabled";
373 clocks = <&tegra_car 41>;
374 };
375
376 spi@7000d600 {
377 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
378 reg = <0x7000d600 0x200>;
379 interrupts = <0 82 0x04>;
380 nvidia,dma-request-selector = <&apbdma 16>;
381 #address-cells = <1>;
382 #size-cells = <0>;
383 status = "disabled";
384 clocks = <&tegra_car 44>;
385 };
386
387 spi@7000d800 {
388 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
389 reg = <0x7000d800 0x200>;
390 interrupts = <0 83 0x04>;
391 nvidia,dma-request-selector = <&apbdma 17>;
392 #address-cells = <1>;
393 #size-cells = <0>;
394 status = "disabled";
395 clocks = <&tegra_car 46>;
396 };
397
398 spi@7000da00 {
399 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
400 reg = <0x7000da00 0x200>;
401 interrupts = <0 93 0x04>;
402 nvidia,dma-request-selector = <&apbdma 18>;
403 #address-cells = <1>;
404 #size-cells = <0>;
405 status = "disabled";
406 clocks = <&tegra_car 68>;
407 };
408
409 spi@7000dc00 {
410 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
411 reg = <0x7000dc00 0x200>;
412 interrupts = <0 94 0x04>;
413 nvidia,dma-request-selector = <&apbdma 27>;
414 #address-cells = <1>;
415 #size-cells = <0>;
416 status = "disabled";
417 clocks = <&tegra_car 104>;
418 };
419
420 spi@7000de00 {
421 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
422 reg = <0x7000de00 0x200>;
423 interrupts = <0 79 0x04>;
424 nvidia,dma-request-selector = <&apbdma 28>;
425 #address-cells = <1>;
426 #size-cells = <0>;
427 status = "disabled";
428 clocks = <&tegra_car 105>;
429 };
430
Simon Glassffc78992015-04-14 21:03:30 -0600431 pmc@7000e400 {
432 compatible = "nvidia,tegra124-pmc";
433 reg = <0x7000e400 0x400>;
434 };
435
Thierry Reding78e9f1c2014-12-09 22:25:10 -0700436 padctl: padctl@7009f000 {
437 compatible = "nvidia,tegra124-xusb-padctl";
438 reg = <0x7009f000 0x1000>;
439 resets = <&tegra_car 142>;
440 reset-names = "padctl";
441
442 #phy-cells = <1>;
443 };
444
Tom Warrena57c5842014-01-24 12:46:17 -0700445 sdhci@700b0000 {
446 compatible = "nvidia,tegra124-sdhci";
447 reg = <0x700b0000 0x200>;
448 interrupts = <0 14 0x04>;
449 clocks = <&tegra_car 14>;
450 status = "disabled";
451 };
452
453 sdhci@700b0200 {
454 compatible = "nvidia,tegra124-sdhci";
455 reg = <0x700b0200 0x200>;
456 interrupts = <0 15 0x04>;
457 clocks = <&tegra_car 9>;
458 status = "disabled";
459 };
460
461 sdhci@700b0400 {
462 compatible = "nvidia,tegra124-sdhci";
463 reg = <0x700b0400 0x200>;
464 interrupts = <0 19 0x04>;
465 clocks = <&tegra_car 69>;
466 status = "disabled";
467 };
468
469 sdhci@700b0600 {
470 compatible = "nvidia,tegra124-sdhci";
471 reg = <0x700b0600 0x200>;
472 interrupts = <0 31 0x04>;
473 clocks = <&tegra_car 15>;
474 status = "disabled";
475 };
476
Simon Glass754204b2014-12-04 06:36:29 -0700477 ahub@70300000 {
478 compatible = "nvidia,tegra124-ahub";
479 reg = <0x70300000 0x200>,
480 <0x70300800 0x800>,
481 <0x70300200 0x600>;
482 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
483 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
484 <&tegra_car TEGRA124_CLK_APBIF>;
485 clock-names = "d_audio", "apbif";
486 resets = <&tegra_car 106>, /* d_audio */
487 <&tegra_car 107>, /* apbif */
488 <&tegra_car 30>, /* i2s0 */
489 <&tegra_car 11>, /* i2s1 */
490 <&tegra_car 18>, /* i2s2 */
491 <&tegra_car 101>, /* i2s3 */
492 <&tegra_car 102>, /* i2s4 */
493 <&tegra_car 108>, /* dam0 */
494 <&tegra_car 109>, /* dam1 */
495 <&tegra_car 110>, /* dam2 */
496 <&tegra_car 10>, /* spdif */
497 <&tegra_car 153>, /* amx */
498 <&tegra_car 185>, /* amx1 */
499 <&tegra_car 154>, /* adx */
500 <&tegra_car 180>, /* adx1 */
501 <&tegra_car 186>, /* afc0 */
502 <&tegra_car 187>, /* afc1 */
503 <&tegra_car 188>, /* afc2 */
504 <&tegra_car 189>, /* afc3 */
505 <&tegra_car 190>, /* afc4 */
506 <&tegra_car 191>; /* afc5 */
507 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
508 "i2s3", "i2s4", "dam0", "dam1", "dam2",
509 "spdif", "amx", "amx1", "adx", "adx1",
510 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
511 dmas = <&apbdma 1>, <&apbdma 1>,
512 <&apbdma 2>, <&apbdma 2>,
513 <&apbdma 3>, <&apbdma 3>,
514 <&apbdma 4>, <&apbdma 4>,
515 <&apbdma 6>, <&apbdma 6>,
516 <&apbdma 7>, <&apbdma 7>,
517 <&apbdma 12>, <&apbdma 12>,
518 <&apbdma 13>, <&apbdma 13>,
519 <&apbdma 14>, <&apbdma 14>,
520 <&apbdma 29>, <&apbdma 29>;
521 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
522 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
523 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
524 "rx9", "tx9";
525 ranges;
526 #address-cells = <1>;
527 #size-cells = <1>;
528
529 tegra_i2s0: i2s@70301000 {
530 compatible = "nvidia,tegra124-i2s";
531 reg = <0x70301000 0x100>;
532 nvidia,ahub-cif-ids = <4 4>;
533 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
534 resets = <&tegra_car 30>;
535 reset-names = "i2s";
536 status = "disabled";
537 };
538
539 tegra_i2s1: i2s@70301100 {
540 compatible = "nvidia,tegra124-i2s";
541 reg = <0x70301100 0x100>;
542 nvidia,ahub-cif-ids = <5 5>;
543 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
544 resets = <&tegra_car 11>;
545 reset-names = "i2s";
546 status = "disabled";
547 };
548
549 tegra_i2s2: i2s@70301200 {
550 compatible = "nvidia,tegra124-i2s";
551 reg = <0x70301200 0x100>;
552 nvidia,ahub-cif-ids = <6 6>;
553 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
554 resets = <&tegra_car 18>;
555 reset-names = "i2s";
556 status = "disabled";
557 };
558
559 tegra_i2s3: i2s@70301300 {
560 compatible = "nvidia,tegra124-i2s";
561 reg = <0x70301300 0x100>;
562 nvidia,ahub-cif-ids = <7 7>;
563 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
564 resets = <&tegra_car 101>;
565 reset-names = "i2s";
566 status = "disabled";
567 };
568
569 tegra_i2s4: i2s@70301400 {
570 compatible = "nvidia,tegra124-i2s";
571 reg = <0x70301400 0x100>;
572 nvidia,ahub-cif-ids = <8 8>;
573 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
574 resets = <&tegra_car 102>;
575 reset-names = "i2s";
576 status = "disabled";
577 };
578 };
579
Tom Warrena57c5842014-01-24 12:46:17 -0700580 usb@7d000000 {
581 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
582 reg = <0x7d000000 0x4000>;
583 interrupts = < 52 >;
584 phy_type = "utmi";
585 clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
586 status = "disabled";
587 };
588
589 usb@7d004000 {
590 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
591 reg = <0x7d004000 0x4000>;
592 interrupts = < 53 >;
593 phy_type = "hsic";
594 clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
595 status = "disabled";
596 };
597
598 usb@7d008000 {
599 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
600 reg = <0x7d008000 0x4000>;
601 interrupts = < 129 >;
602 phy_type = "utmi";
603 clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
604 status = "disabled";
605 };
606};