blob: b128e46c2766953c4148f77a0d6750fbd9a02cb2 [file] [log] [blame]
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001/*
2 * (C) Copyright 2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 * Port to AMCC-440SPE Evaluation Board SOP - April 2005
Rafal Jaworowski692519b2006-08-10 12:43:17 +020024 *
25 * PCIe supporting routines derived from Linux 440SPe PCIe driver.
Marian Balakowicz6c5879f2006-06-30 16:30:46 +020026 */
27
28#include <common.h>
Stefan Roeseb36df562010-09-09 19:18:00 +020029#include <asm/ppc4xx.h>
Marian Balakowicz6c5879f2006-06-30 16:30:46 +020030#include <i2c.h>
Ben Warren10efa022008-08-31 20:37:00 -070031#include <netdev.h>
Stefan Roesec7c6da22007-10-03 07:34:10 +020032#include <asm/processor.h>
33#include <asm/io.h>
34#include <asm/4xx_pcie.h>
Stefan Roese06dfaee2009-10-02 14:35:16 +020035#include <asm/errno.h>
Rafal Jaworowski692519b2006-08-10 12:43:17 +020036
Marian Balakowicz6c5879f2006-06-30 16:30:46 +020037#include "yucca.h"
Stefan Roese2b393b02006-08-29 08:05:15 +020038
Wolfgang Denk1218abf2007-09-15 20:48:41 +020039DECLARE_GLOBAL_DATA_PTR;
40
Marian Balakowicz6c5879f2006-06-30 16:30:46 +020041void fpga_init (void);
Marian Balakowicz6c5879f2006-06-30 16:30:46 +020042
43#define DEBUG_ENV
44#ifdef DEBUG_ENV
45#define DEBUGF(fmt,args...) printf(fmt ,##args)
46#else
47#define DEBUGF(fmt,args...)
48#endif
49
50#define FALSE 0
51#define TRUE 1
52
53int board_early_init_f (void)
54{
55/*----------------------------------------------------------------------------+
56| Define Boot devices
57+----------------------------------------------------------------------------*/
58#define BOOT_FROM_SMALL_FLASH 0x00
59#define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01
60#define BOOT_FROM_PCI 0x02
61#define BOOT_DEVICE_UNKNOWN 0x03
62
63/*----------------------------------------------------------------------------+
64| EBC Devices Characteristics
65| Peripheral Bank Access Parameters - EBC_BxAP
66| Peripheral Bank Configuration Register - EBC_BxCR
67+----------------------------------------------------------------------------*/
68
69/*
70 * Small Flash and FRAM
71 * BU Value
72 * BxAP : 0x03800000 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
73 * B0CR : 0xff098000 - BAS = ff0 - 100 11 00 0000000000000
74 * B2CR : 0xe7098000 - BAS = e70 - 100 11 00 0000000000000
75 */
76#define EBC_BXAP_SMALL_FLASH EBC_BXAP_BME_DISABLED | \
77 EBC_BXAP_TWT_ENCODE(7) | \
78 EBC_BXAP_BCE_DISABLE | \
79 EBC_BXAP_BCT_2TRANS | \
80 EBC_BXAP_CSN_ENCODE(0) | \
81 EBC_BXAP_OEN_ENCODE(0) | \
82 EBC_BXAP_WBN_ENCODE(0) | \
83 EBC_BXAP_WBF_ENCODE(0) | \
84 EBC_BXAP_TH_ENCODE(0) | \
85 EBC_BXAP_RE_DISABLED | \
86 EBC_BXAP_SOR_DELAYED | \
87 EBC_BXAP_BEM_WRITEONLY | \
88 EBC_BXAP_PEN_DISABLED
89
90#define EBC_BXCR_SMALL_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \
91 EBC_BXCR_BS_16MB | \
92 EBC_BXCR_BU_RW | \
93 EBC_BXCR_BW_8BIT
94
95#define EBC_BXCR_SMALL_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xe7000000) | \
96 EBC_BXCR_BS_16MB | \
97 EBC_BXCR_BU_RW | \
98 EBC_BXCR_BW_8BIT
99
100/*
101 * Large Flash and SRAM
102 * BU Value
103 * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
104 * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000
105 * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000
106*/
107#define EBC_BXAP_LARGE_FLASH EBC_BXAP_BME_DISABLED | \
108 EBC_BXAP_TWT_ENCODE(7) | \
109 EBC_BXAP_BCE_DISABLE | \
110 EBC_BXAP_BCT_2TRANS | \
111 EBC_BXAP_CSN_ENCODE(0) | \
112 EBC_BXAP_OEN_ENCODE(0) | \
113 EBC_BXAP_WBN_ENCODE(0) | \
114 EBC_BXAP_WBF_ENCODE(0) | \
115 EBC_BXAP_TH_ENCODE(0) | \
116 EBC_BXAP_RE_DISABLED | \
117 EBC_BXAP_SOR_DELAYED | \
118 EBC_BXAP_BEM_WRITEONLY | \
119 EBC_BXAP_PEN_DISABLED
120
121#define EBC_BXCR_LARGE_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \
122 EBC_BXCR_BS_16MB | \
123 EBC_BXCR_BU_RW | \
124 EBC_BXCR_BW_16BIT
125
126#define EBC_BXCR_LARGE_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xE7000000) | \
127 EBC_BXCR_BS_16MB | \
128 EBC_BXCR_BU_RW | \
129 EBC_BXCR_BW_16BIT
130
131/*
132 * FPGA
133 * BU value :
134 * B1AP = 0x05895240 - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
135 * B1CR = 0xe201a000 - BAS = e20 - 000 11 01 00000000000000
136 */
137#define EBC_BXAP_FPGA EBC_BXAP_BME_DISABLED | \
138 EBC_BXAP_TWT_ENCODE(11) | \
139 EBC_BXAP_BCE_DISABLE | \
140 EBC_BXAP_BCT_2TRANS | \
141 EBC_BXAP_CSN_ENCODE(10) | \
142 EBC_BXAP_OEN_ENCODE(1) | \
143 EBC_BXAP_WBN_ENCODE(1) | \
144 EBC_BXAP_WBF_ENCODE(1) | \
145 EBC_BXAP_TH_ENCODE(1) | \
146 EBC_BXAP_RE_DISABLED | \
147 EBC_BXAP_SOR_DELAYED | \
148 EBC_BXAP_BEM_RW | \
149 EBC_BXAP_PEN_DISABLED
150
151#define EBC_BXCR_FPGA_CS1 EBC_BXCR_BAS_ENCODE(0xe2000000) | \
152 EBC_BXCR_BS_1MB | \
153 EBC_BXCR_BU_RW | \
154 EBC_BXCR_BW_16BIT
155
156 unsigned long mfr;
157 /*
158 * Define Variables for EBC initialization depending on BOOTSTRAP option
159 */
160 unsigned long sdr0_pinstp, sdr0_sdstp1 ;
161 unsigned long bootstrap_settings, ebc_data_width, boot_selection;
162 int computed_boot_device = BOOT_DEVICE_UNKNOWN;
163
164 /*-------------------------------------------------------------------+
165 | Initialize EBC CONFIG -
166 | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
167 | default value :
168 | 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
169 |
170 +-------------------------------------------------------------------*/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200171 mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200172 EBC_CFG_PTD_ENABLE |
173 EBC_CFG_RTC_16PERCLK |
174 EBC_CFG_ATC_PREVIOUS |
175 EBC_CFG_DTC_PREVIOUS |
176 EBC_CFG_CTC_PREVIOUS |
177 EBC_CFG_OEO_PREVIOUS |
178 EBC_CFG_EMC_DEFAULT |
179 EBC_CFG_PME_DISABLE |
180 EBC_CFG_PR_16);
181
182 /*-------------------------------------------------------------------+
183 |
184 | PART 1 : Initialize EBC Bank 1
185 | ==============================
186 | Bank1 is always associated to the EPLD.
187 | It has to be initialized prior to other banks settings computation
188 | since some board registers values may be needed to determine the
189 | boot type
190 |
191 +-------------------------------------------------------------------*/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200192 mtebc(PB1AP, EBC_BXAP_FPGA);
193 mtebc(PB1CR, EBC_BXCR_FPGA_CS1);
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200194
195 /*-------------------------------------------------------------------+
196 |
197 | PART 2 : Determine which boot device was selected
198 | =================================================
199 |
200 | Read Pin Strap Register in PPC440SPe
201 | Result can either be :
202 | - Boot strap = boot from EBC 8bits => Small Flash
203 | - Boot strap = boot from PCI
204 | - Boot strap = IIC
205 | In case of boot from IIC, read Serial Device Strap Register1
206 |
207 | Result can either be :
208 | - Boot from EBC - EBC Bus Width = 8bits => Small Flash
209 | - Boot from EBC - EBC Bus Width = 16bits => Large Flash or SRAM
210 | - Boot from PCI
211 |
212 +-------------------------------------------------------------------*/
213 /* Read Pin Strap Register in PPC440SP */
Stefan Roese2f5df472007-03-08 10:10:18 +0100214 mfsdr(SDR0_PINSTP, sdr0_pinstp);
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200215 bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK;
216
217 switch (bootstrap_settings) {
218 case SDR0_PINSTP_BOOTSTRAP_SETTINGS0:
219 /*
220 * Strapping Option A
221 * Boot from EBC - 8 bits , Small Flash
222 */
223 computed_boot_device = BOOT_FROM_SMALL_FLASH;
224 break;
225 case SDR0_PINSTP_BOOTSTRAP_SETTINGS1:
226 /*
227 * Strappping Option B
228 * Boot from PCI
229 */
230 computed_boot_device = BOOT_FROM_PCI;
231 break;
232 case SDR0_PINSTP_BOOTSTRAP_IIC_50_EN:
233 case SDR0_PINSTP_BOOTSTRAP_IIC_54_EN:
234 /*
235 * Strapping Option C or D
236 * Boot Settings in IIC EEprom address 0x50 or 0x54
237 * Read Serial Device Strap Register1 in PPC440SPe
238 */
Stefan Roese2f5df472007-03-08 10:10:18 +0100239 mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200240 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK;
241 ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK;
242
243 switch (boot_selection) {
244 case SDR0_SDSTP1_ERPN_EBC:
245 switch (ebc_data_width) {
246 case SDR0_SDSTP1_EBCW_16_BITS:
247 computed_boot_device =
248 BOOT_FROM_LARGE_FLASH_OR_SRAM;
249 break;
250 case SDR0_SDSTP1_EBCW_8_BITS :
251 computed_boot_device = BOOT_FROM_SMALL_FLASH;
252 break;
253 }
254 break;
255
256 case SDR0_SDSTP1_ERPN_PCI:
257 computed_boot_device = BOOT_FROM_PCI;
258 break;
259 default:
260 /* should not occure */
261 computed_boot_device = BOOT_DEVICE_UNKNOWN;
262 }
263 break;
264 default:
265 /* should not be */
266 computed_boot_device = BOOT_DEVICE_UNKNOWN;
267 break;
268 }
269
270 /*-------------------------------------------------------------------+
271 |
272 | PART 3 : Compute EBC settings depending on selected boot device
273 | ====== ======================================================
274 |
275 | Resulting EBC init will be among following configurations :
276 |
277 | - Boot from EBC 8bits => boot from Small Flash selected
278 | EBC-CS0 = Small Flash
279 | EBC-CS2 = Large Flash and SRAM
280 |
281 | - Boot from EBC 16bits => boot from Large Flash or SRAM
282 | EBC-CS0 = Large Flash or SRAM
283 | EBC-CS2 = Small Flash
284 |
285 | - Boot from PCI
286 | EBC-CS0 = not initialized to avoid address contention
287 | EBC-CS2 = same as boot from Small Flash selected
288 |
289 +-------------------------------------------------------------------*/
290 unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
291 unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
292
293 switch (computed_boot_device) {
294 /*-------------------------------------------------------------------*/
295 case BOOT_FROM_PCI:
296 /*-------------------------------------------------------------------*/
297 /*
298 * By Default CS2 is affected to LARGE Flash
299 * do not initialize SMALL FLASH to avoid address contention
300 * Large Flash
301 */
302 ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH;
303 ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
304 break;
305
306 /*-------------------------------------------------------------------*/
307 case BOOT_FROM_SMALL_FLASH:
308 /*-------------------------------------------------------------------*/
309 ebc0_cs0_bxap_value = EBC_BXAP_SMALL_FLASH;
310 ebc0_cs0_bxcr_value = EBC_BXCR_SMALL_FLASH_CS0;
311
312 /*
313 * Large Flash or SRAM
314 */
315 /* ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; */
316 ebc0_cs2_bxap_value = 0x048ff240;
317 ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
318 break;
319
320 /*-------------------------------------------------------------------*/
321 case BOOT_FROM_LARGE_FLASH_OR_SRAM:
322 /*-------------------------------------------------------------------*/
323 ebc0_cs0_bxap_value = EBC_BXAP_LARGE_FLASH;
324 ebc0_cs0_bxcr_value = EBC_BXCR_LARGE_FLASH_CS0;
325
326 /* Small flash */
327 ebc0_cs2_bxap_value = EBC_BXAP_SMALL_FLASH;
328 ebc0_cs2_bxcr_value = EBC_BXCR_SMALL_FLASH_CS2;
329 break;
330
331 /*-------------------------------------------------------------------*/
332 default:
333 /*-------------------------------------------------------------------*/
334 /* BOOT_DEVICE_UNKNOWN */
335 break;
336 }
337
Stefan Roesed1c3b272009-09-09 16:25:29 +0200338 mtebc(PB0AP, ebc0_cs0_bxap_value);
339 mtebc(PB0CR, ebc0_cs0_bxcr_value);
340 mtebc(PB2AP, ebc0_cs2_bxap_value);
341 mtebc(PB2CR, ebc0_cs2_bxcr_value);
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200342
343 /*--------------------------------------------------------------------+
344 | Interrupt controller setup for the AMCC 440SPe Evaluation board.
345 +--------------------------------------------------------------------+
346 +---------------------------------------------------------------------+
347 |Interrupt| Source | Pol. | Sensi.| Crit. |
348 +---------+-----------------------------------+-------+-------+-------+
349 | IRQ 00 | UART0 | High | Level | Non |
350 | IRQ 01 | UART1 | High | Level | Non |
351 | IRQ 02 | IIC0 | High | Level | Non |
352 | IRQ 03 | IIC1 | High | Level | Non |
353 | IRQ 04 | PCI0X0 MSG IN | High | Level | Non |
354 | IRQ 05 | PCI0X0 CMD Write | High | Level | Non |
355 | IRQ 06 | PCI0X0 Power Mgt | High | Level | Non |
356 | IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non |
357 | IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non |
358 | IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non |
359 | IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non |
360 | IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit |
361 | IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non |
362 | IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non |
363 | IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non |
364 | IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non |
365 | IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non |
366 | IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit |
367 | IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non |
368 | IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non |
369 | IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non |
370 | IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non |
371 | IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non |
372 | IRQ 23 | I2O Inbound Doorbell | High | Level | Non |
373 | IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non |
374 | IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non |
375 | IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non |
376 | IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non |
377 | IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non |
378 | IRQ 29 | GPT Down Count Timer | Rising| Edge | Non |
379 | IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non |
380 | IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. |
381 |----------------------------------------------------------------------
382 | IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non |
383 | IRQ 33 | MAL Serr | High | Level | Non |
384 | IRQ 34 | MAL Txde | High | Level | Non |
385 | IRQ 35 | MAL Rxde | High | Level | Non |
386 | IRQ 36 | DMC CE or DMC UE | High | Level | Non |
387 | IRQ 37 | EBC or UART2 | High |Lvl Edg| Non |
388 | IRQ 38 | MAL TX EOB | High | Level | Non |
389 | IRQ 39 | MAL RX EOB | High | Level | Non |
390 | IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non |
391 | IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non |
392 | IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non |
393 | IRQ 43 | L2 Cache | Risin | Edge | Non |
394 | IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non |
395 | IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non |
396 | IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non |
397 | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
398 | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
399 | IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non |
400 | IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non |
401 | IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non |
402 | IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
403 | IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non |
404 | IRQ 54 | DMA Error | High | Level | Non |
405 | IRQ 55 | DMA I2O Error | High | Level | Non |
406 | IRQ 56 | Serial ROM | High | Level | Non |
407 | IRQ 57 | PCIX0 Error | High | Edge | Non |
408 | IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non |
409 | IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non |
410 | IRQ 60 | EMAC0 Interrupt | High | Level | Non |
411 | IRQ 61 | EMAC0 Wake-up | High | Level | Non |
412 | IRQ 62 | Reserved | High | Level | Non |
413 | IRQ 63 | XOR | High | Level | Non |
414 |----------------------------------------------------------------------
415 | IRQ 64 | PE0 AL | High | Level | Non |
416 | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
417 | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
418 | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
419 | IRQ 68 | PE0 TCR | High | Level | Non |
420 | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
421 | IRQ 70 | PE0 DCR Error | High | Level | Non |
422 | IRQ 71 | Reserved | N/A | N/A | Non |
423 | IRQ 72 | PE1 AL | High | Level | Non |
424 | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
425 | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
426 | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
427 | IRQ 76 | PE1 TCR | High | Level | Non |
428 | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
429 | IRQ 78 | PE1 DCR Error | High | Level | Non |
430 | IRQ 79 | Reserved | N/A | N/A | Non |
431 | IRQ 80 | PE2 AL | High | Level | Non |
432 | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
433 | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
434 | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
435 | IRQ 84 | PE2 TCR | High | Level | Non |
436 | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
437 | IRQ 86 | PE2 DCR Error | High | Level | Non |
438 | IRQ 87 | Reserved | N/A | N/A | Non |
439 | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
440 | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
441 | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
442 | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
443 | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
444 | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
445 | IRQ 94 | Reserved | N/A | N/A | Non |
446 | IRQ 95 | Reserved | N/A | N/A | Non |
447 |---------------------------------------------------------------------
448 | IRQ 96 | PE0 INTA | High | Level | Non |
449 | IRQ 97 | PE0 INTB | High | Level | Non |
450 | IRQ 98 | PE0 INTC | High | Level | Non |
451 | IRQ 99 | PE0 INTD | High | Level | Non |
452 | IRQ 100 | PE1 INTA | High | Level | Non |
453 | IRQ 101 | PE1 INTB | High | Level | Non |
454 | IRQ 102 | PE1 INTC | High | Level | Non |
455 | IRQ 103 | PE1 INTD | High | Level | Non |
456 | IRQ 104 | PE2 INTA | High | Level | Non |
457 | IRQ 105 | PE2 INTB | High | Level | Non |
458 | IRQ 106 | PE2 INTC | High | Level | Non |
459 | IRQ 107 | PE2 INTD | Risin | Edge | Non |
460 | IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non |
461 | IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non |
462 | IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non |
463 | IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non |
464 | IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non |
465 | IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non |
466 | IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non |
467 | IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non |
468 | IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non |
469 | IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non |
470 | IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non |
471 | IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non |
472 | IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non |
473 | IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non |
474 | IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non |
475 | IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non |
476 | IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non |
477 | IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non |
478 | IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non |
479 | IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non |
480 +---------+-----------------------------------+-------+-------+------*/
481 /*--------------------------------------------------------------------+
482 | Put UICs in PowerPC440SPemode.
483 | Initialise UIC registers. Clear all interrupts. Disable all
484 | interrupts.
485 | Set critical interrupt values. Set interrupt polarities. Set
486 | interrupt trigger levels. Make bit 0 High priority. Clear all
487 | interrupts again.
488 +-------------------------------------------------------------------*/
Stefan Roese952e7762009-09-24 09:55:50 +0200489 mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */
490 mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */
491 mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200492 * interrupts */
Stefan Roese952e7762009-09-24 09:55:50 +0200493 mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities */
494 mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */
495 mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200496 * priority */
Stefan Roese952e7762009-09-24 09:55:50 +0200497 mtdcr (UIC3SR, 0x00000000); /* clear all interrupts */
498 mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200499
Stefan Roese952e7762009-09-24 09:55:50 +0200500 mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
501 mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */
502 mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200503 * interrupts */
Stefan Roese952e7762009-09-24 09:55:50 +0200504 mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities */
505 mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */
506 mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200507 * priority */
Stefan Roese952e7762009-09-24 09:55:50 +0200508 mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
509 mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200510
Stefan Roese952e7762009-09-24 09:55:50 +0200511 mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */
512 mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */
513 mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200514 * interrupts */
Stefan Roese952e7762009-09-24 09:55:50 +0200515 mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */
516 mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels */
517 mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200518 * priority */
Stefan Roese952e7762009-09-24 09:55:50 +0200519 mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */
520 mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200521
Stefan Roese952e7762009-09-24 09:55:50 +0200522 mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
523 mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200524 * cascade to be checked */
Stefan Roese952e7762009-09-24 09:55:50 +0200525 mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200526 * interrupts */
Stefan Roese952e7762009-09-24 09:55:50 +0200527 mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities */
528 mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */
529 mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200530 * priority */
Stefan Roese952e7762009-09-24 09:55:50 +0200531 mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */
532 mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200533
Stefan Roesed1c3b272009-09-09 16:25:29 +0200534 mfsdr(SDR0_MFR, mfr);
Stefan Roesea27044b2007-12-06 05:58:43 +0100535 mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200536 mtsdr(SDR0_MFR, mfr);
Stefan Roesea27044b2007-12-06 05:58:43 +0100537
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200538 fpga_init();
539
540 return 0;
541}
542
543int checkboard (void)
544{
Marian Balakowiczfe84b482006-07-03 23:42:36 +0200545 char *s = getenv("serial#");
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200546
Marian Balakowiczfe84b482006-07-03 23:42:36 +0200547 printf("Board: Yucca - AMCC 440SPe Evaluation Board");
548 if (s != NULL) {
549 puts(", serial# ");
550 puts(s);
551 }
552 putc('\n');
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200553
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200554 return 0;
555}
556
Stefan Roesedf3f1742007-07-16 10:00:43 +0200557/*
Stefan Roesea47a12b2010-04-15 16:07:28 +0200558 * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
Stefan Roesedf3f1742007-07-16 10:00:43 +0200559 * board specific values.
560 */
561static int ppc440spe_rev_a(void)
562{
563 if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA))
564 return 1;
565 else
566 return 0;
567}
568
569u32 ddr_wrdtr(u32 default_val) {
570 /*
571 * Yucca boards with 440SPe rev. A need a slightly different setup
572 * for the MCIF0_WRDTR register.
573 */
574 if (ppc440spe_rev_a())
575 return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV);
576
577 return default_val;
578}
579
580u32 ddr_clktr(u32 default_val) {
581 /*
582 * Yucca boards with 440SPe rev. A need a slightly different setup
583 * for the MCIF0_CLKTR register.
584 */
585 if (ppc440spe_rev_a())
586 return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
587
588 return default_val;
589}
590
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200591#if defined(CONFIG_PCI)
Stefan Roeseb0b86742009-10-29 15:04:35 +0100592int board_pcie_card_present(int port)
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200593{
594 u16 reg;
595
596 reg = in_be16((u16 *)FPGA_REG1C);
597 switch(port) {
598 case 0:
599 return !(reg & FPGA_REG1C_PE0_PRSNT);
600 case 1:
601 return !(reg & FPGA_REG1C_PE1_PRSNT);
602 case 2:
603 return !(reg & FPGA_REG1C_PE2_PRSNT);
604 default:
605 return 0;
606 }
607}
608
609/*
Stefan Roese2b393b02006-08-29 08:05:15 +0200610 * For the given slot, set endpoint mode, send power to the slot,
Stefan Roeseb0b86742009-10-29 15:04:35 +0100611 * turn on the green LED and turn off the yellow LED, enable the
Peter Tyser64917ca2010-01-17 15:38:26 -0600612 * clock. In endpoint mode reset bit is read only.
Stefan Roese2b393b02006-08-29 08:05:15 +0200613 */
Stefan Roeseb0b86742009-10-29 15:04:35 +0100614void board_pcie_setup_port(int port, int rootpoint)
Stefan Roese2b393b02006-08-29 08:05:15 +0200615{
Stefan Roeseb0b86742009-10-29 15:04:35 +0100616 u16 power, clock, green_led, yellow_led,
617 reset_off, rp, ep;
Stefan Roese2b393b02006-08-29 08:05:15 +0200618
Stefan Roeseb0b86742009-10-29 15:04:35 +0100619 switch (port) {
Stefan Roese2b393b02006-08-29 08:05:15 +0200620 case 0:
Stefan Roeseb0b86742009-10-29 15:04:35 +0100621 rp = FPGA_REG1C_PE0_ROOTPOINT;
622 ep = 0;
Stefan Roese2b393b02006-08-29 08:05:15 +0200623 break;
624 case 1:
Stefan Roeseb0b86742009-10-29 15:04:35 +0100625 rp = 0;
626 ep = FPGA_REG1C_PE1_ENDPOINT;
Stefan Roese2b393b02006-08-29 08:05:15 +0200627 break;
628 case 2:
Stefan Roeseb0b86742009-10-29 15:04:35 +0100629 rp = 0;
630 ep = FPGA_REG1C_PE2_ENDPOINT;
Stefan Roese2b393b02006-08-29 08:05:15 +0200631 break;
632
633 default:
634 return;
635 }
636
Stefan Roeseb0b86742009-10-29 15:04:35 +0100637 power = FPGA_REG1A_PWRON_ENCODE(port);
638 green_led = FPGA_REG1A_GLED_ENCODE(port);
639 clock = FPGA_REG1A_REFCLK_ENCODE(port);
640 yellow_led = FPGA_REG1A_YLED_ENCODE(port);
641 reset_off = FPGA_REG1C_PERST_ENCODE(port);
642
643 out_be16((u16 *)FPGA_REG1A, ~(power | clock | green_led) &
Stefan Roese2b393b02006-08-29 08:05:15 +0200644 (yellow_led | in_be16((u16 *)FPGA_REG1A)));
645
Stefan Roeseb0b86742009-10-29 15:04:35 +0100646 out_be16((u16 *)FPGA_REG1C, ~(ep | reset_off) &
647 (rp | in_be16((u16 *)FPGA_REG1C)));
Stefan Roese2b393b02006-08-29 08:05:15 +0200648
Stefan Roeseb0b86742009-10-29 15:04:35 +0100649 if (rootpoint) {
650 /*
651 * Leave device in reset for a while after powering on the
652 * slot to give it a chance to initialize.
653 */
654 udelay(250 * 1000);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200655
Stefan Roeseb0b86742009-10-29 15:04:35 +0100656 out_be16((u16 *)FPGA_REG1C,
657 reset_off | in_be16((u16 *)FPGA_REG1C));
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200658 }
659}
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200660#endif /* defined(CONFIG_PCI) */
661
662int misc_init_f (void)
663{
664 uint reg;
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200665
666 out16(FPGA_REG10, (in16(FPGA_REG10) &
667 ~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
668 FPGA_REG10_10MHZ_ENABLE |
669 FPGA_REG10_100MHZ_ENABLE |
670 FPGA_REG10_GIGABIT_ENABLE |
671 FPGA_REG10_FULL_DUPLEX );
672
673 udelay(10000); /* wait 10ms */
674
675 out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH));
676
677 /* minimal init for PCIe */
678 /* pci express 0 Endpoint Mode */
Stefan Roesed9056b72008-06-30 14:05:05 +0200679 mfsdr(SDRN_PESDR_DLPSET(0), reg);
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200680 reg &= (~0x00400000);
Stefan Roesed9056b72008-06-30 14:05:05 +0200681 mtsdr(SDRN_PESDR_DLPSET(0), reg);
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200682 /* pci express 1 Rootpoint Mode */
Stefan Roesed9056b72008-06-30 14:05:05 +0200683 mfsdr(SDRN_PESDR_DLPSET(1), reg);
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200684 reg |= 0x00400000;
Stefan Roesed9056b72008-06-30 14:05:05 +0200685 mtsdr(SDRN_PESDR_DLPSET(1), reg);
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200686 /* pci express 2 Rootpoint Mode */
Stefan Roesed9056b72008-06-30 14:05:05 +0200687 mfsdr(SDRN_PESDR_DLPSET(2), reg);
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200688 reg |= 0x00400000;
Stefan Roesed9056b72008-06-30 14:05:05 +0200689 mtsdr(SDRN_PESDR_DLPSET(2), reg);
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200690
691 out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
692 ~FPGA_REG1C_PE0_ROOTPOINT &
693 ~FPGA_REG1C_PE1_ENDPOINT &
694 ~FPGA_REG1C_PE2_ENDPOINT));
695
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200696 return 0;
697}
698
699void fpga_init(void)
700{
701 /*
702 * by default sdram access is disabled by fpga
703 */
704 out16(FPGA_REG10, (in16 (FPGA_REG10) |
705 FPGA_REG10_SDRAM_ENABLE |
706 FPGA_REG10_ENABLE_DISPLAY ));
707
708 return;
709}
710
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200711/*---------------------------------------------------------------------------+
712 | onboard_pci_arbiter_selected => from EPLD
713 +---------------------------------------------------------------------------*/
714int onboard_pci_arbiter_selected(int core_pci)
715{
716#if 0
717 unsigned long onboard_pci_arbiter_sel;
718
719 onboard_pci_arbiter_sel = in16(FPGA_REG0) & FPGA_REG0_EXT_ARB_SEL_MASK;
720
721 if (onboard_pci_arbiter_sel == FPGA_REG0_EXT_ARB_SEL_EXTERNAL)
722 return (BOARD_OPTION_SELECTED);
723 else
724#endif
725 return (BOARD_OPTION_NOT_SELECTED);
726}
Ben Warren10efa022008-08-31 20:37:00 -0700727
728int board_eth_init(bd_t *bis)
729{
Stefan Roesecef0efa2009-02-11 09:29:33 +0100730 cpu_eth_init(bis);
Ben Warren10efa022008-08-31 20:37:00 -0700731 return pci_eth_init(bis);
732}