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Stefan Roese887e2ec2006-09-07 11:51:23 +02001/*
Stefan Roesefc84a842008-03-07 08:01:43 +01002 * (C) Copyright 2006-2008
Stefan Roese887e2ec2006-09-07 11:51:23 +02003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2006
6 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
7 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
8 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese887e2ec2006-09-07 11:51:23 +020010 */
11
Larry Johnson214398d2008-01-18 21:49:05 -050012/*
Stefan Roesee8025942007-01-30 17:06:10 +010013 * sequoia.h - configuration for Sequoia & Rainier boards
Larry Johnson214398d2008-01-18 21:49:05 -050014 */
Stefan Roese887e2ec2006-09-07 11:51:23 +020015#ifndef __CONFIG_H
16#define __CONFIG_H
17
Larry Johnson214398d2008-01-18 21:49:05 -050018/*
Stefan Roese887e2ec2006-09-07 11:51:23 +020019 * High Level Configuration Options
Larry Johnson214398d2008-01-18 21:49:05 -050020 */
Stefan Roesee8025942007-01-30 17:06:10 +010021/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */
Stefan Roese854bc8d2006-09-13 13:51:58 +020022#ifndef CONFIG_RAINIER
Larry Johnson214398d2008-01-18 21:49:05 -050023#define CONFIG_440EPX 1 /* Specific PPC440EPx */
Stefan Roese72675dc2008-06-06 15:55:21 +020024#define CONFIG_HOSTNAME sequoia
Stefan Roese854bc8d2006-09-13 13:51:58 +020025#else
Larry Johnson214398d2008-01-18 21:49:05 -050026#define CONFIG_440GRX 1 /* Specific PPC440GRx */
Stefan Roese72675dc2008-06-06 15:55:21 +020027#define CONFIG_HOSTNAME rainier
Stefan Roese854bc8d2006-09-13 13:51:58 +020028#endif
Larry Johnson214398d2008-01-18 21:49:05 -050029#define CONFIG_440 1 /* ... PPC440 family */
Stefan Roese72675dc2008-06-06 15:55:21 +020030
Wolfgang Denk2ae18242010-10-06 09:05:45 +020031#ifndef CONFIG_SYS_TEXT_BASE
32#define CONFIG_SYS_TEXT_BASE 0xFFF80000
33#endif
34
Stefan Roese72675dc2008-06-06 15:55:21 +020035/*
36 * Include common defines/options for all AMCC eval boards
37 */
38#include "amcc-common.h"
39
Jeffrey Manne3b8c782007-05-05 08:32:14 +020040/* Detect Sequoia PLL input clock automatically via CPLD bit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_CLK_FREQ ((in8(CONFIG_SYS_BCSR_BASE + 3) & 0x80) ? \
Jeffrey Mann193b4a32007-05-07 19:42:49 +020042 33333333 : 33000000)
Stefan Roese887e2ec2006-09-07 11:51:23 +020043
Anatolij Gustschinbc778812008-02-21 12:52:29 +010044/*
45 * Define this if you want support for video console with radeon 9200 pci card
Wolfgang Denk14d0a022010-10-07 21:51:12 +020046 * Also set CONFIG_SYS_TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case
Anatolij Gustschinbc778812008-02-21 12:52:29 +010047 */
48#undef CONFIG_VIDEO
49
50#ifdef CONFIG_VIDEO
Stefan Roesed25dfe02007-10-31 17:57:52 +010051/*
52 * 44x dcache supported is working now on sequoia, but we don't enable
53 * it yet since it needs further testing
54 */
Larry Johnson214398d2008-01-18 21:49:05 -050055#define CONFIG_4xx_DCACHE /* enable dcache */
Stefan Roesed25dfe02007-10-31 17:57:52 +010056#endif
57
Larry Johnson214398d2008-01-18 21:49:05 -050058#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
59#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
Stefan Roese887e2ec2006-09-07 11:51:23 +020060
Larry Johnson214398d2008-01-18 21:49:05 -050061/*
62 * Base addresses -- Note these are effective addresses where the actual
63 * resources get mapped (not physical addresses).
64 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0x0003
66#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
67#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
68#define CONFIG_SYS_NAND_ADDR 0xd0000000 /* NAND Flash */
69#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
70#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
71#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
72#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
73#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
74#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
75#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
Stefan Roese887e2ec2006-09-07 11:51:23 +020076
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_USB2D0_BASE 0xe0000100
78#define CONFIG_SYS_USB_DEVICE 0xe0000000
79#define CONFIG_SYS_USB_HOST 0xe0000400
80#define CONFIG_SYS_BCSR_BASE 0xc0000000
Stefan Roese887e2ec2006-09-07 11:51:23 +020081
Larry Johnson214398d2008-01-18 21:49:05 -050082/*
Stefan Roese887e2ec2006-09-07 11:51:23 +020083 * Initial RAM & stack pointer
Larry Johnson214398d2008-01-18 21:49:05 -050084 */
Stefan Roese887e2ec2006-09-07 11:51:23 +020085/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
Wolfgang Denk553f0982010-10-26 13:32:32 +020087#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020088#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Michael Zaidman800eb092010-09-20 08:51:53 +020089#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
Stefan Roese887e2ec2006-09-07 11:51:23 +020090
Larry Johnson214398d2008-01-18 21:49:05 -050091/*
Stefan Roese887e2ec2006-09-07 11:51:23 +020092 * Serial Port
Larry Johnson214398d2008-01-18 21:49:05 -050093 */
Stefan Roese550650d2010-09-20 16:05:31 +020094#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
Stefan Roese887e2ec2006-09-07 11:51:23 +020096
Larry Johnson214398d2008-01-18 21:49:05 -050097/*
Stefan Roese887e2ec2006-09-07 11:51:23 +020098 * Environment
Larry Johnson214398d2008-01-18 21:49:05 -050099 */
Stefan Roese345b77b2014-03-04 15:34:35 +0100100#if defined(CONFIG_SYS_RAMBOOT)
Stefan Roesed8731332009-05-11 13:46:14 +0200101#define CONFIG_ENV_IS_NOWHERE /* Store env in memory only */
102#define CONFIG_ENV_SIZE (8 << 10)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200103#else
Stefan Roesed8731332009-05-11 13:46:14 +0200104#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environ vars */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200105#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +0200106
Stefan Roesed8731332009-05-11 13:46:14 +0200107#if defined(CONFIG_CMD_FLASH)
Larry Johnson214398d2008-01-18 21:49:05 -0500108/*
Stefan Roese887e2ec2006-09-07 11:51:23 +0200109 * FLASH related
Larry Johnson214398d2008-01-18 21:49:05 -0500110 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200112#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Stefan Roese887e2ec2006-09-07 11:51:23 +0200115
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
117#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200118
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
120#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
123#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
126#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200127
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200128#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200129#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200131#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200132
133/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200134#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
135#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200136#endif
Stefan Roesed8731332009-05-11 13:46:14 +0200137#endif /* CONFIG_CMD_FLASH */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200138
Stefan Roese887e2ec2006-09-07 11:51:23 +0200139/*
Stefan Roese887e2ec2006-09-07 11:51:23 +0200140 * DDR SDRAM
Larry Johnson214398d2008-01-18 21:49:05 -0500141 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
Stefan Roese345b77b2014-03-04 15:34:35 +0100143#if !defined(CONFIG_SYS_RAMBOOT)
Larry Johnson214398d2008-01-18 21:49:05 -0500144#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
Stefan Roese02388982007-01-05 10:38:05 +0100145#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
Stefan Roese14f73ca2008-03-26 10:14:11 +0100147 /* 440EPx errata CHIP 11 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200148
Larry Johnson214398d2008-01-18 21:49:05 -0500149/*
Stefan Roese887e2ec2006-09-07 11:51:23 +0200150 * I2C
Larry Johnson214398d2008-01-18 21:49:05 -0500151 */
Dirk Eibach880540d2013-04-25 02:40:01 +0000152#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
Stefan Roese887e2ec2006-09-07 11:51:23 +0200153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_I2C_MULTI_EEPROMS
155#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
156#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
157#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
158#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Stefan Roese887e2ec2006-09-07 11:51:23 +0200159
Stefan Roesecfc25872009-10-19 16:19:36 +0200160/* I2C bootstrap EEPROM */
161#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
162#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
163#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
164
Stefan Roese887e2ec2006-09-07 11:51:23 +0200165/* I2C SYSMON (LM75, AD7414 is almost compatible) */
Larry Johnson214398d2008-01-18 21:49:05 -0500166#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
167#define CONFIG_DTT_AD7414 1 /* use AD7414 */
168#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_DTT_MAX_TEMP 70
170#define CONFIG_SYS_DTT_LOW_TEMP -30
171#define CONFIG_SYS_DTT_HYSTERESIS 3
Stefan Roese887e2ec2006-09-07 11:51:23 +0200172
Stefan Roese72675dc2008-06-06 15:55:21 +0200173/*
174 * Default environment variables
175 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200176#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roese72675dc2008-06-06 15:55:21 +0200177 CONFIG_AMCC_DEF_ENV \
178 CONFIG_AMCC_DEF_ENV_POWERPC \
179 CONFIG_AMCC_DEF_ENV_PPC_OLD \
180 CONFIG_AMCC_DEF_ENV_NOR_UPD \
Stefan Roese4ef62512006-11-20 20:39:52 +0100181 "kernel_addr=FC000000\0" \
182 "ramdisk_addr=FC180000\0" \
Stefan Roese887e2ec2006-09-07 11:51:23 +0200183 ""
Stefan Roese887e2ec2006-09-07 11:51:23 +0200184
185#define CONFIG_M88E1111_PHY 1
186#define CONFIG_IBM_EMAC4_V4 1
Stefan Roese887e2ec2006-09-07 11:51:23 +0200187#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
188
Larry Johnson214398d2008-01-18 21:49:05 -0500189#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200190#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
191
192#define CONFIG_HAS_ETH0
Stefan Roese887e2ec2006-09-07 11:51:23 +0200193#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
194#define CONFIG_PHY1_ADDR 1
195
196/* USB */
Stefan Roese854bc8d2006-09-13 13:51:58 +0200197#ifdef CONFIG_440EPX
Chris Zhang559e2c82010-01-06 13:34:06 -0800198
199#undef CONFIG_USB_EHCI /* OHCI by default */
200
201#ifdef CONFIG_USB_EHCI
202#define CONFIG_USB_EHCI_PPC4XX
203#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
204#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
205#define CONFIG_EHCI_MMIO_BIG_ENDIAN
206#define CONFIG_EHCI_DESC_BIG_ENDIAN
Chris Zhang559e2c82010-01-06 13:34:06 -0800207#else /* CONFIG_USB_EHCI */
Matthias Fuchs2d146842007-11-09 15:37:53 +0100208#define CONFIG_USB_OHCI_NEW
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_OHCI_BE_CONTROLLER
Matthias Fuchs2d146842007-11-09 15:37:53 +0100210
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
212#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
213#define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
214#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
215#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
Chris Zhang559e2c82010-01-06 13:34:06 -0800216#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +0200217
Chris Zhang559e2c82010-01-06 13:34:06 -0800218#define CONFIG_USB_STORAGE
Stefan Roese887e2ec2006-09-07 11:51:23 +0200219/* Comment this out to enable USB 1.1 device */
220#define USB_2_0_DEVICE
221
Stefan Roese854bc8d2006-09-13 13:51:58 +0200222#endif /* CONFIG_440EPX */
223
Stefan Roese887e2ec2006-09-07 11:51:23 +0200224/* Partitions */
225#define CONFIG_MAC_PARTITION
226#define CONFIG_DOS_PARTITION
227#define CONFIG_ISO_PARTITION
228
Jon Loeliger46da1e92007-07-04 22:33:30 -0500229/*
Stefan Roese72675dc2008-06-06 15:55:21 +0200230 * Commands additional to the ones defined in amcc-common.h
Jon Loeliger079a1362007-07-10 10:12:10 -0500231 */
Stefan Roesecfc25872009-10-19 16:19:36 +0200232#define CONFIG_CMD_CHIP_CONFIG
Jon Loeliger46da1e92007-07-04 22:33:30 -0500233#define CONFIG_CMD_DTT
Jon Loeliger46da1e92007-07-04 22:33:30 -0500234#define CONFIG_CMD_FAT
Jon Loeliger46da1e92007-07-04 22:33:30 -0500235#define CONFIG_CMD_NAND
Jon Loeliger46da1e92007-07-04 22:33:30 -0500236#define CONFIG_CMD_PCI
Jon Loeliger46da1e92007-07-04 22:33:30 -0500237#define CONFIG_CMD_SDRAM
238
239#ifdef CONFIG_440EPX
240#define CONFIG_CMD_USB
241#endif
242
Stefan Roese9de469b2007-08-16 10:18:33 +0200243#ifndef CONFIG_RAINIER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_POST_FPU_ON CONFIG_SYS_POST_FPU
Stefan Roese9de469b2007-08-16 10:18:33 +0200245#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_POST_FPU_ON 0
Stefan Roese9de469b2007-08-16 10:18:33 +0200247#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +0200248
Stefan Roese9a929172009-04-15 14:06:26 +0200249/*
250 * Don't run the memory POST on the NAND-booting version. It will
251 * overwrite part of the U-Boot image which is already loaded from NAND
252 * to SDRAM.
253 */
Stefan Roese345b77b2014-03-04 15:34:35 +0100254#if defined(CONFIG_SYS_RAMBOOT)
Stefan Roese9a929172009-04-15 14:06:26 +0200255#define CONFIG_SYS_POST_MEMORY_ON 0
256#else
257#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
258#endif
259
Igor Lisitsina11e0692007-03-28 19:06:19 +0400260/* POST support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
262 CONFIG_SYS_POST_CPU | \
263 CONFIG_SYS_POST_ETHER | \
Stefan Roese9a929172009-04-15 14:06:26 +0200264 CONFIG_SYS_POST_FPU_ON | \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265 CONFIG_SYS_POST_I2C | \
Stefan Roese9a929172009-04-15 14:06:26 +0200266 CONFIG_SYS_POST_MEMORY_ON | \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267 CONFIG_SYS_POST_SPR | \
268 CONFIG_SYS_POST_UART)
Igor Lisitsina11e0692007-03-28 19:06:19 +0400269
Igor Lisitsina11e0692007-03-28 19:06:19 +0400270#define CONFIG_LOGBUFFER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
Igor Lisitsina11e0692007-03-28 19:06:19 +0400272
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
Igor Lisitsina11e0692007-03-28 19:06:19 +0400274
Stefan Roese887e2ec2006-09-07 11:51:23 +0200275#define CONFIG_SUPPORT_VFAT
276
Larry Johnson214398d2008-01-18 21:49:05 -0500277/*
Stefan Roese887e2ec2006-09-07 11:51:23 +0200278 * PCI stuff
Larry Johnson214398d2008-01-18 21:49:05 -0500279 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200280/* General PCI */
Larry Johnson214398d2008-01-18 21:49:05 -0500281#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000282#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Larry Johnson214398d2008-01-18 21:49:05 -0500283#define CONFIG_PCI_PNP /* do pci plug-and-play */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
Larry Johnson214398d2008-01-18 21:49:05 -0500285#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
287 /* CONFIG_SYS_PCI_MEMBASE */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200288/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_PCI_TARGET_INIT
290#define CONFIG_SYS_PCI_MASTER_INIT
Stefan Roesea760b022009-11-12 16:41:09 +0100291#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
Stefan Roese887e2ec2006-09-07 11:51:23 +0200292
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
294#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200295
296/*
Stefan Roese887e2ec2006-09-07 11:51:23 +0200297 * External Bus Controller (EBC) Setup
Larry Johnson214398d2008-01-18 21:49:05 -0500298 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200299
300/*
301 * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
302 */
Stefan Roese345b77b2014-03-04 15:34:35 +0100303#if !defined(CONFIG_SYS_RAMBOOT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
Larry Johnson214398d2008-01-18 21:49:05 -0500305/* Memory Bank 0 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_EBC_PB0AP 0x03017200
307#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200308
Larry Johnson214398d2008-01-18 21:49:05 -0500309/* Memory Bank 3 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_EBC_PB3AP 0x018003c0
311#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200312#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
Larry Johnson214398d2008-01-18 21:49:05 -0500314/* Memory Bank 3 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_EBC_PB3AP 0x03017200
316#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FLASH_BASE | 0xda000)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200317
Larry Johnson214398d2008-01-18 21:49:05 -0500318/* Memory Bank 0 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_EBC_PB0AP 0x018003c0
320#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200321#endif
322
Larry Johnson214398d2008-01-18 21:49:05 -0500323/* Memory Bank 2 (CPLD) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_EBC_PB2AP 0x24814580
325#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_BCSR_BASE | 0x38000)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200326
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_BCSR5_PCI66EN 0x80
Stefan Roese5a5958b2007-10-15 11:29:33 +0200328
Larry Johnson214398d2008-01-18 21:49:05 -0500329/*
Stefan Roese43a2b0e2006-10-20 14:28:52 +0200330 * NAND FLASH
Larry Johnson214398d2008-01-18 21:49:05 -0500331 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_MAX_NAND_DEVICE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
334#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
Stefan Roese43a2b0e2006-10-20 14:28:52 +0200335
Larry Johnson214398d2008-01-18 21:49:05 -0500336/*
Lawrence R. Johnsonb05e8bf2008-01-04 02:11:56 -0500337 * PPC440 GPIO Configuration
338 */
339/* test-only: take GPIO init from pcs440ep ???? in config file */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
Lawrence R. Johnsonb05e8bf2008-01-04 02:11:56 -0500341{ \
342/* GPIO Core 0 */ \
343{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
344{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
345{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
346{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
347{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
348{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
349{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
350{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
351{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
352{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
353{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
354{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
355{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
356{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
357{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO14 */ \
358{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
359{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \
360{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \
361{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \
362{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \
363{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
364{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
365{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
366{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
367{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \
368{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \
369{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
370{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
371{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO28 USB2D_TXVALID */ \
372{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
373{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
374{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
375}, \
376{ \
377/* GPIO Core 1 */ \
378{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
379{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
Steven A. Falcoeab10072008-08-06 15:42:52 -0400380{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_8PIN_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
381{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
382{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_CTS_N EBC_DATA(0) UART3_SIN*/ \
383{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
384{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_8PIN_DTR_N UART1_SOUT */ \
385{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_8PIN_RI_N UART1_SIN */ \
Lawrence R. Johnsonb05e8bf2008-01-04 02:11:56 -0500386{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
387{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
388{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
389{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
390{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
391{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
392{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
393{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
394{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
395{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
396{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
397{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
398{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
399{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
400{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
401{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
402{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
403{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
404{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
405{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
406{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
407{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
408{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
409{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
410} \
411}
412
Anatolij Gustschinbc778812008-02-21 12:52:29 +0100413#ifdef CONFIG_VIDEO
414#define CONFIG_BIOSEMU /* x86 bios emulator for vga bios */
415#define CONFIG_ATI_RADEON_FB /* use radeon framebuffer driver */
416#define VIDEO_IO_OFFSET 0xe8000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
Anatolij Gustschinbc778812008-02-21 12:52:29 +0100418#define CONFIG_VIDEO_SW_CURSOR
419#define CONFIG_VIDEO_LOGO
420#define CONFIG_CFB_CONSOLE
421#define CONFIG_SPLASH_SCREEN
422#define CONFIG_VGA_AS_SINGLE_DEVICE
423#define CONFIG_CMD_BMP
424#endif
425
Larry Johnson214398d2008-01-18 21:49:05 -0500426#endif /* __CONFIG_H */