wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 1 | /* |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 2 | * |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 3 | * (C) Copyright 2002 |
| 4 | * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>. |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | */ |
| 24 | |
| 25 | #include <common.h> |
| 26 | #include <pci.h> |
Ben Warren | 10efa02 | 2008-08-31 20:37:00 -0700 | [diff] [blame] | 27 | #include <netdev.h> |
Graeme Russ | 91ee4e1 | 2009-08-23 12:59:54 +1000 | [diff] [blame] | 28 | #include <ds1722.h> |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 29 | #include <asm/io.h> |
| 30 | #include <asm/pci.h> |
| 31 | #include <asm/ic/sc520.h> |
Graeme Russ | 91ee4e1 | 2009-08-23 12:59:54 +1000 | [diff] [blame] | 32 | #include <asm/ic/pci.h> |
| 33 | #include <asm/ic/ssi.h> |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 34 | |
Wolfgang Denk | d87080b | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 35 | DECLARE_GLOBAL_DATA_PTR; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 36 | |
| 37 | /* |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 38 | * Theory: |
| 39 | * We first set up all IRQs to be non-pci, edge triggered, |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 40 | * when we later enumerate the pci bus and pci_sc520_fixup_irq() gets |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 41 | * called we reallocate irqs to the pci bus with sc520_pci_set_irq() |
| 42 | * as needed. Whe choose the irqs to gram from a configurable list |
| 43 | * inside pci_sc520_fixup_irq() (If this list contains stupid irq's |
| 44 | * such as 0 thngas will not work) |
| 45 | */ |
| 46 | |
| 47 | static void irq_init(void) |
| 48 | { |
| 49 | /* disable global interrupt mode */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 50 | write_mmcr_byte(SC520_PICICR, 0x40); |
| 51 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 52 | /* set all irqs to edge */ |
| 53 | write_mmcr_byte(SC520_MPICMODE, 0x00); |
| 54 | write_mmcr_byte(SC520_SL1PICMODE, 0x00); |
| 55 | write_mmcr_byte(SC520_SL2PICMODE, 0x00); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 56 | |
| 57 | /* active low polarity on PIC interrupt pins, |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 58 | * active high polarity on all other irq pins */ |
| 59 | write_mmcr_word(SC520_INTPINPOL, 0x0000); |
| 60 | |
| 61 | /* set irq number mapping */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 62 | write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED); /* disable GP timer 0 INT */ |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 63 | write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED); /* disable GP timer 1 INT */ |
| 64 | write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED); /* disable GP timer 2 INT */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 65 | write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0); /* Set PIT timer 0 INT to IRQ0 */ |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 66 | write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED); /* disable PIT timer 1 INT */ |
| 67 | write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED); /* disable PIT timer 2 INT */ |
| 68 | write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED); /* disable PCI INT A */ |
| 69 | write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED); /* disable PCI INT B */ |
| 70 | write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED); /* disable PCI INT C */ |
| 71 | write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED); /* disable PCI INT D */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 72 | write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */ |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 73 | write_mmcr_byte(SC520_SSIMAP, SC520_IRQ6); /* Set Synchronius serial INT to IRQ6*/ |
| 74 | write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED); /* disable Watchdog INT */ |
| 75 | write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8); /* Set RTC int to 8 */ |
| 76 | write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED); /* disable write protect INT */ |
| 77 | write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1); /* Set ICE Debug Serielport INT to IRQ1 */ |
| 78 | write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13); /* Set FP error INT to IRQ13 */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 79 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 80 | write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4); /* Set internal UART2 INT to IRQ4 */ |
| 81 | write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3); /* Set internal UART2 INT to IRQ3 */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 82 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 83 | write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ7); /* Set GPIRQ0 (PC-Card AUX IRQ) to IRQ7 */ |
| 84 | write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ14); /* Set GPIRQ1 (CF IRQ) to IRQ14 */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 85 | write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ5); /* Set GPIRQ3 ( CAN IRQ ) ti IRQ5 */ |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 86 | write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED); /* disbale GIRQ4 ( IRR IRQ ) */ |
| 87 | write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ5 */ |
| 88 | write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ6 */ |
| 89 | write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ7 */ |
| 90 | write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ8 */ |
| 91 | write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ9 */ |
| 92 | write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ2 */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 93 | write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ_DISABLED); /* disable GPIRQ10 */ |
| 94 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 95 | write_mmcr_word(SC520_PCIHOSTMAP, 0x11f); /* Map PCI hostbridge INT to NMI */ |
| 96 | write_mmcr_word(SC520_ECCMAP, 0x100); /* Map SDRAM ECC failure INT to NMI */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 97 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 98 | } |
| 99 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 100 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 101 | /* PCI stuff */ |
| 102 | static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev) |
| 103 | { |
| 104 | int version = read_mmcr_byte(SC520_SYSINFO); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 105 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 106 | /* a configurable lists of irqs to steal |
| 107 | * when we need one (a board with more pci interrupt pins |
| 108 | * would use a larger table */ |
| 109 | static int irq_list[] = { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 110 | CONFIG_SYS_FIRST_PCI_IRQ, |
| 111 | CONFIG_SYS_SECOND_PCI_IRQ, |
| 112 | CONFIG_SYS_THIRD_PCI_IRQ, |
| 113 | CONFIG_SYS_FORTH_PCI_IRQ |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 114 | }; |
| 115 | static int next_irq_index=0; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 116 | |
Graeme Russ | 91ee4e1 | 2009-08-23 12:59:54 +1000 | [diff] [blame] | 117 | uchar tmp_pin; |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 118 | int pin; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 119 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 120 | pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin); |
| 121 | pin = tmp_pin; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 122 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 123 | pin-=1; /* pci config space use 1-based numbering */ |
| 124 | if (-1 == pin) { |
| 125 | return; /* device use no irq */ |
| 126 | } |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 127 | |
| 128 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 129 | /* map device number + pin to a pin on the sc520 */ |
| 130 | switch (PCI_DEV(dev)) { |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 131 | case 6: /* ETH0 */ |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 132 | pin+=SC520_PCI_INTA; |
| 133 | break; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 134 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 135 | case 7: /* ETH1 */ |
| 136 | pin+=SC520_PCI_INTB; |
| 137 | break; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 138 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 139 | case 8: /* Crypto */ |
| 140 | pin+=SC520_PCI_INTC; |
| 141 | break; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 142 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 143 | case 9: /* PMC slot */ |
| 144 | pin+=SC520_PCI_INTD; |
| 145 | break; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 146 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 147 | case 10: /* PC-Card */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 148 | |
| 149 | if (version < 10) { |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 150 | pin+=SC520_PCI_INTD; |
| 151 | } else { |
| 152 | pin+=SC520_PCI_INTC; |
| 153 | } |
| 154 | break; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 155 | |
| 156 | default: |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 157 | return; |
| 158 | } |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 159 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 160 | pin&=3; /* wrap around */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 161 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 162 | if (sc520_pci_ints[pin] == -1) { |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 163 | /* re-route one interrupt for us */ |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 164 | if (next_irq_index > 3) { |
| 165 | return; |
| 166 | } |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 167 | if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) { |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 168 | return; |
| 169 | } |
| 170 | next_irq_index++; |
| 171 | } |
| 172 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 173 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 174 | if (-1 != sc520_pci_ints[pin]) { |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 175 | pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 176 | sc520_pci_ints[pin]); |
| 177 | } |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 178 | #if 0 |
| 179 | printf("fixup_irq: device %d pin %c irq %d\n", |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 180 | PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]); |
| 181 | #endif |
| 182 | } |
| 183 | |
| 184 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 185 | static void pci_sc520_spunk_configure_cardbus(struct pci_controller *hose, |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 186 | pci_dev_t dev, struct pci_config_table *te) |
| 187 | { |
| 188 | u32 io_base; |
| 189 | u32 temp; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 190 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 191 | pciauto_config_device(hose, dev); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 192 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 193 | pci_hose_write_config_word(hose, dev, PCI_COMMAND, 0x07); /* enable device */ |
| 194 | pci_hose_write_config_byte(hose, dev, 0x0c, 0x10); /* cacheline size */ |
| 195 | pci_hose_write_config_byte(hose, dev, 0x0d, 0x40); /* latency timer */ |
| 196 | pci_hose_write_config_byte(hose, dev, 0x1b, 0x40); /* cardbus latency timer */ |
| 197 | pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0040); /* reset cardbus */ |
| 198 | pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0080); /* route interrupts though ExCA */ |
| 199 | pci_hose_write_config_word(hose, dev, 0x44, 0x3e0); /* map legacy I/O port to 0x3e0 */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 200 | |
| 201 | pci_hose_read_config_dword(hose, dev, 0x80, &temp); /* System control */ |
| 202 | pci_hose_write_config_dword(hose, dev, 0x80, temp | 0x60); /* System control: disable clockrun */ |
| 203 | /* route MF0 to ~INT and MF3 to IRQ7 |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 204 | * reserve all others */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 205 | pci_hose_write_config_dword(hose, dev, 0x8c, 0x00007002); |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 206 | pci_hose_write_config_byte(hose, dev, 0x91, 0x00); /* card control */ |
| 207 | pci_hose_write_config_byte(hose, dev, 0x92, 0x62); /* device control */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 208 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 209 | if (te->device != 0xac56) { |
| 210 | pci_hose_write_config_byte(hose, dev, 0x93, 0x21); /* async interrupt enable */ |
| 211 | pci_hose_write_config_word(hose, dev, 0xa8, 0x0000); /* reset GPIO */ |
| 212 | pci_hose_write_config_word(hose, dev, 0xac, 0x0000); /* reset GPIO */ |
| 213 | pci_hose_write_config_word(hose, dev, 0xaa, 0x0000); /* reset GPIO */ |
| 214 | pci_hose_write_config_word(hose, dev, 0xae, 0x0000); /* reset GPIO */ |
| 215 | } else { |
| 216 | pci_hose_write_config_byte(hose, dev, 0x93, 0x20); /* */ |
| 217 | } |
| 218 | pci_hose_write_config_word(hose, dev, 0xa4, 0x8000); /* reset power management */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 219 | |
| 220 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 221 | pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &io_base); |
| 222 | io_base &= ~0xfL; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 223 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 224 | writeb(0x07, io_base+0x803); /* route CSC irq though ExCA and enable IRQ7 */ |
| 225 | writel(0, io_base+0x10); /* CLKRUN default */ |
| 226 | writel(0, io_base+0x20); /* CLKRUN default */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 227 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 228 | } |
| 229 | |
| 230 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 231 | static struct pci_config_table pci_sc520_spunk_config_table[] = { |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 232 | { 0x104c, 0xac50, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} }, |
| 233 | { 0x104c, 0xac56, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} }, |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 234 | { 0, 0, 0, 0, 0, 0, NULL, {0,0,0}} |
| 235 | }; |
| 236 | |
| 237 | static struct pci_controller sc520_spunk_hose = { |
| 238 | fixup_irq: pci_sc520_spunk_fixup_irq, |
| 239 | config_table: pci_sc520_spunk_config_table, |
| 240 | first_busno: 0x00, |
| 241 | last_busno: 0xff, |
| 242 | }; |
| 243 | |
| 244 | void pci_init_board(void) |
| 245 | { |
| 246 | pci_sc520_init(&sc520_spunk_hose); |
| 247 | } |
| 248 | |
| 249 | |
| 250 | /* set up the ISA bus timing and system address mappings */ |
| 251 | static void bus_init(void) |
| 252 | { |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 253 | /* versions |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 254 | * 0 Hyglo versions 0.95 and 0.96 (large baords) |
| 255 | * ?? Hyglo version 0.97 (small board) |
| 256 | * 10 Spunk board |
| 257 | */ |
| 258 | int version = read_mmcr_byte(SC520_SYSINFO); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 259 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 260 | if (version) { |
| 261 | /* set up the GP IO pins (for the Spunk board) */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 262 | write_mmcr_word(SC520_PIOPFS31_16, 0xfff0); /* set the GPIO pin function 31-16 reg */ |
| 263 | write_mmcr_word(SC520_PIOPFS15_0, 0x000f); /* set the GPIO pin function 15-0 reg */ |
| 264 | write_mmcr_word(SC520_PIODIR31_16, 0x000f); /* set the GPIO direction 31-16 reg */ |
| 265 | write_mmcr_word(SC520_PIODIR15_0, 0x1ff0); /* set the GPIO direction 15-0 reg */ |
| 266 | write_mmcr_byte(SC520_CSPFS, 0xc0); /* set the CS pin function reg */ |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 267 | write_mmcr_byte(SC520_CLKSEL, 0x70); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 268 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 269 | write_mmcr_word(SC520_PIOCLR31_16, 0x0003); /* reset SSI chip-selects */ |
| 270 | write_mmcr_word(SC520_PIOSET31_16, 0x000c); |
| 271 | |
| 272 | } else { |
| 273 | /* set up the GP IO pins (for the Hyglo board) */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 274 | write_mmcr_word(SC520_PIOPFS31_16, 0xffc0); /* set the GPIO pin function 31-16 reg */ |
| 275 | write_mmcr_word(SC520_PIOPFS15_0, 0x1e7f); /* set the GPIO pin function 15-0 reg */ |
| 276 | write_mmcr_word(SC520_PIODIR31_16, 0x003f); /* set the GPIO direction 31-16 reg */ |
| 277 | write_mmcr_word(SC520_PIODIR15_0, 0xe180); /* set the GPIO direction 15-0 reg */ |
| 278 | write_mmcr_byte(SC520_CSPFS, 0x00); /* set the CS pin function reg */ |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 279 | write_mmcr_byte(SC520_CLKSEL, 0x70); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 280 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 281 | write_mmcr_word(SC520_PIOCLR15_0, 0x0180); /* reset SSI chip-selects */ |
| 282 | } |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 283 | |
| 284 | write_mmcr_byte(SC520_GPCSRT, 1); /* set the GP CS offset */ |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 285 | write_mmcr_byte(SC520_GPCSPW, 3); /* set the GP CS pulse width */ |
| 286 | write_mmcr_byte(SC520_GPCSOFF, 1); /* set the GP CS offset */ |
| 287 | write_mmcr_byte(SC520_GPRDW, 3); /* set the RD pulse width */ |
| 288 | write_mmcr_byte(SC520_GPRDOFF, 1); /* set the GP RD offset */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 289 | write_mmcr_byte(SC520_GPWRW, 3); /* set the GP WR pulse width */ |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 290 | write_mmcr_byte(SC520_GPWROFF, 1); /* set the GP WR offset */ |
| 291 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 292 | write_mmcr_word(SC520_BOOTCSCTL, 0x0407); /* set up timing of BOOTCS */ |
| 293 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 294 | /* adjust the memory map: |
| 295 | * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM |
| 296 | * and 256MB to 1G-128k (0x1000000 - 0x37ffffff) is mapped to PCI mmio |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 297 | * we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */ |
| 298 | |
| 299 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 300 | /* bootcs */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 301 | write_mmcr_long(SC520_PAR12, 0x8bffe800); |
| 302 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 303 | /* IDE0 = GPCS6 1f0-1f7 */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 304 | write_mmcr_long(SC520_PAR3, 0x380801f0); |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 305 | |
| 306 | /* IDE1 = GPCS7 3f6 */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 307 | write_mmcr_long(SC520_PAR4, 0x3c0003f6); |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 308 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 309 | asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */ |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 310 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 311 | write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS)); |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 312 | |
| 313 | } |
| 314 | |
| 315 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 316 | /* par usage: |
| 317 | * PAR0 (legacy_video) |
| 318 | * PAR1 (PCI ROM mapping) |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 319 | * PAR2 |
| 320 | * PAR3 IDE |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 321 | * PAR4 IDE |
| 322 | * PAR5 (legacy_video) |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 323 | * PAR6 |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 324 | * PAR7 (legacy_video) |
| 325 | * PAR8 (legacy_video) |
| 326 | * PAR9 (legacy_video) |
| 327 | * PAR10 |
| 328 | * PAR11 (ISAROM) |
| 329 | * PAR12 BOOTCS |
| 330 | * PAR13 |
| 331 | * PAR14 |
| 332 | * PAR15 |
| 333 | */ |
| 334 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 335 | /* |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 336 | * This function should map a chunk of size bytes |
| 337 | * of the system address space to the ISA bus |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 338 | * |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 339 | * The function will return the memory address |
| 340 | * as seen by the host (which may very will be the |
| 341 | * same as the bus address) |
| 342 | */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 343 | u32 isa_map_rom(u32 bus_addr, int size) |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 344 | { |
| 345 | u32 par; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 346 | |
| 347 | printf("isa_map_rom asked to map %d bytes at %x\n", |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 348 | size, bus_addr); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 349 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 350 | par = size; |
| 351 | if (par < 0x80000) { |
| 352 | par = 0x80000; |
| 353 | } |
| 354 | par >>= 12; |
| 355 | par--; |
| 356 | par&=0x7f; |
| 357 | par <<= 18; |
| 358 | par |= (bus_addr>>12); |
| 359 | par |= 0x50000000; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 360 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 361 | printf ("setting PAR11 to %x\n", par); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 362 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 363 | /* Map rom 0x10000 with PAR1 */ |
| 364 | write_mmcr_long(SC520_PAR11, par); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 365 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 366 | return bus_addr; |
| 367 | } |
| 368 | |
| 369 | /* |
| 370 | * this function removed any mapping created |
| 371 | * with pci_get_rom_window() |
| 372 | */ |
| 373 | void isa_unmap_rom(u32 addr) |
| 374 | { |
| 375 | printf("isa_unmap_rom asked to unmap %x", addr); |
| 376 | if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) { |
| 377 | write_mmcr_long(SC520_PAR11, 0); |
| 378 | printf(" done\n"); |
| 379 | return; |
| 380 | } |
| 381 | printf(" not ours\n"); |
| 382 | } |
| 383 | |
| 384 | #ifdef CONFIG_PCI |
| 385 | #define PCI_ROM_TEMP_SPACE 0x10000 |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 386 | /* |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 387 | * This function should map a chunk of size bytes |
| 388 | * of the system address space to the PCI bus, |
| 389 | * suitable to map PCI ROMS (bus address < 16M) |
| 390 | * the function will return the host memory address |
| 391 | * which should be converted into a bus address |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 392 | * before used to configure the PCI rom address |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 393 | * decoder |
| 394 | */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 395 | u32 pci_get_rom_window(struct pci_controller *hose, int size) |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 396 | { |
| 397 | u32 par; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 398 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 399 | par = size; |
| 400 | if (par < 0x80000) { |
| 401 | par = 0x80000; |
| 402 | } |
| 403 | par >>= 16; |
| 404 | par--; |
| 405 | par&=0x7ff; |
| 406 | par <<= 14; |
| 407 | par |= (PCI_ROM_TEMP_SPACE>>16); |
| 408 | par |= 0x72000000; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 409 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 410 | printf ("setting PAR1 to %x\n", par); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 411 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 412 | /* Map rom 0x10000 with PAR1 */ |
| 413 | write_mmcr_long(SC520_PAR1, par); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 414 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 415 | return PCI_ROM_TEMP_SPACE; |
| 416 | } |
| 417 | |
| 418 | /* |
| 419 | * this function removed any mapping created |
| 420 | * with pci_get_rom_window() |
| 421 | */ |
| 422 | void pci_remove_rom_window(struct pci_controller *hose, u32 addr) |
| 423 | { |
| 424 | printf("pci_remove_rom_window: %x", addr); |
| 425 | if (addr == PCI_ROM_TEMP_SPACE) { |
| 426 | write_mmcr_long(SC520_PAR1, 0); |
| 427 | printf(" done\n"); |
| 428 | return; |
| 429 | } |
| 430 | printf(" not ours\n"); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 431 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 432 | } |
| 433 | |
| 434 | /* |
| 435 | * This function is called in order to provide acces to the |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 436 | * legacy video I/O ports on the PCI bus. |
| 437 | * After this function accesses to I/O ports 0x3b0-0x3bb and |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 438 | * 0x3c0-0x3df shuld result in transactions on the PCI bus. |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 439 | * |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 440 | */ |
| 441 | int pci_enable_legacy_video_ports(struct pci_controller *hose) |
| 442 | { |
| 443 | /* Map video memory to 0xa0000*/ |
| 444 | write_mmcr_long(SC520_PAR0, 0x7200400a); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 445 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 446 | /* forward all I/O accesses to PCI */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 447 | write_mmcr_byte(SC520_ADDDECCTL, |
| 448 | read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI); |
| 449 | |
| 450 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 451 | /* so we map away all io ports to pci (only way to access pci io |
| 452 | * below 0x400. But then we have to map back the portions that we dont |
| 453 | * use so that the generate cycles on the GPIO bus where the sio and |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 454 | * ISA slots are connected, this requre the use of several PAR registers |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 455 | */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 456 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 457 | /* bring 0x100 - 0x2f7 back to ISA using PAR5 */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 458 | write_mmcr_long(SC520_PAR5, 0x31f70100); |
| 459 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 460 | /* com2 use 2f8-2ff */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 461 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 462 | /* bring 0x300 - 0x3af back to ISA using PAR7 */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 463 | write_mmcr_long(SC520_PAR7, 0x30af0300); |
| 464 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 465 | /* vga use 3b0-3bb */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 466 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 467 | /* bring 0x3bc - 0x3bf back to ISA using PAR8 */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 468 | write_mmcr_long(SC520_PAR8, 0x300303bc); |
| 469 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 470 | /* vga use 3c0-3df */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 471 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 472 | /* bring 0x3e0 - 0x3f7 back to ISA using PAR9 */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 473 | write_mmcr_long(SC520_PAR9, 0x301703e0); |
| 474 | |
| 475 | /* com1 use 3f8-3ff */ |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 476 | |
| 477 | return 0; |
| 478 | } |
| 479 | #endif |
| 480 | |
| 481 | /* |
| 482 | * Miscelaneous platform dependent initialisations |
| 483 | */ |
| 484 | |
| 485 | int board_init(void) |
| 486 | { |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 487 | init_sc520(); |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 488 | bus_init(); |
| 489 | irq_init(); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 490 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 491 | /* max drive current on SDRAM */ |
| 492 | write_mmcr_word(SC520_DSCTL, 0x0100); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 493 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 494 | /* enter debug mode after next reset (only if jumper is also set) */ |
| 495 | write_mmcr_byte(SC520_RESCFG, 0x08); |
| 496 | /* configure the software timer to 33.000MHz */ |
| 497 | write_mmcr_byte(SC520_SWTMRCFG, 1); |
| 498 | gd->bus_clk = 33000000; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 499 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 500 | return 0; |
| 501 | } |
| 502 | |
| 503 | int dram_init(void) |
| 504 | { |
| 505 | init_sc520_dram(); |
| 506 | return 0; |
| 507 | } |
| 508 | |
| 509 | void show_boot_progress(int val) |
| 510 | { |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 511 | int version = read_mmcr_byte(SC520_SYSINFO); |
| 512 | |
Heiko Schocher | 566a494 | 2007-06-22 19:11:54 +0200 | [diff] [blame] | 513 | if (val < -32) val = -1; /* let things compatible */ |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 514 | if (version == 0) { |
| 515 | /* PIO31-PIO16 Data */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 516 | write_mmcr_word(SC520_PIODATA31_16, |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 517 | (read_mmcr_word(SC520_PIODATA31_16) & 0xffc0)| ((val&0x7e)>>1)); /* 0x1f8 >> 3 */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 518 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 519 | /* PIO0-PIO15 Data */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 520 | write_mmcr_word(SC520_PIODATA15_0, |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 521 | (read_mmcr_word(SC520_PIODATA15_0) & 0x1fff)| ((val&0x7)<<13)); |
| 522 | } else { |
| 523 | /* newer boards use PIO4-PIO12 */ |
| 524 | /* PIO0-PIO15 Data */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 525 | #if 0 |
| 526 | val = (val & 0x007) | ((val & 0x038) << 3) | ((val & 0x1c0) >> 3); |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 527 | #else |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 528 | val = (val & 0x007) | ((val & 0x07e) << 2); |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 529 | #endif |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 530 | write_mmcr_word(SC520_PIODATA15_0, |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 531 | (read_mmcr_word(SC520_PIODATA15_0) & 0xe00f) | ((val&0x01ff)<<4)); |
| 532 | } |
| 533 | } |
| 534 | |
| 535 | |
| 536 | int last_stage_init(void) |
| 537 | { |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 538 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 539 | int version = read_mmcr_byte(SC520_SYSINFO); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 540 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 541 | printf("Omicron Ceti SC520 Spunk revision %x\n", version); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 542 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 543 | #if 0 |
| 544 | if (version) { |
| 545 | int x, y; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 546 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 547 | printf("eeprom probe %d\n", spi_eeprom_probe(1)); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 548 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 549 | spi_eeprom_read(1, 0, (u8*)&x, 2); |
| 550 | spi_eeprom_read(1, 1, (u8*)&y, 2); |
| 551 | printf("eeprom bytes %04x%04x\n", x, y); |
| 552 | x ^= 0xffff; |
| 553 | y ^= 0xffff; |
| 554 | spi_eeprom_write(1, 0, (u8*)&x, 2); |
| 555 | spi_eeprom_write(1, 1, (u8*)&y, 2); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 556 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 557 | spi_eeprom_read(1, 0, (u8*)&x, 2); |
| 558 | spi_eeprom_read(1, 1, (u8*)&y, 2); |
| 559 | printf("eeprom bytes %04x%04x\n", x, y); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 560 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 561 | } else { |
| 562 | int x, y; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 563 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 564 | printf("eeprom probe %d\n", mw_eeprom_probe(1)); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 565 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 566 | mw_eeprom_read(1, 0, (u8*)&x, 2); |
| 567 | mw_eeprom_read(1, 1, (u8*)&y, 2); |
| 568 | printf("eeprom bytes %04x%04x\n", x, y); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 569 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 570 | x ^= 0xffff; |
| 571 | y ^= 0xffff; |
| 572 | mw_eeprom_write(1, 0, (u8*)&x, 2); |
| 573 | mw_eeprom_write(1, 1, (u8*)&y, 2); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 574 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 575 | mw_eeprom_read(1, 0, (u8*)&x, 2); |
| 576 | mw_eeprom_read(1, 1, (u8*)&y, 2); |
| 577 | printf("eeprom bytes %04x%04x\n", x, y); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 578 | |
| 579 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 580 | } |
| 581 | #endif |
| 582 | |
| 583 | ds1722_probe(2); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 584 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 585 | return 0; |
| 586 | } |
| 587 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 588 | void ssi_chip_select(int dev) |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 589 | { |
| 590 | int version = read_mmcr_byte(SC520_SYSINFO); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 591 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 592 | if (version) { |
| 593 | /* Spunk board: EEPROM and CAN are actove-low, TEMP and AUX are active high */ |
| 594 | switch (dev) { |
| 595 | case 1: /* EEPROM */ |
| 596 | write_mmcr_word(SC520_PIOCLR31_16, 0x0004); |
| 597 | break; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 598 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 599 | case 2: /* Temp Probe */ |
| 600 | write_mmcr_word(SC520_PIOSET31_16, 0x0002); |
| 601 | break; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 602 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 603 | case 3: /* CAN */ |
| 604 | write_mmcr_word(SC520_PIOCLR31_16, 0x0008); |
| 605 | break; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 606 | |
| 607 | case 4: /* AUX */ |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 608 | write_mmcr_word(SC520_PIOSET31_16, 0x0001); |
| 609 | break; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 610 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 611 | case 0: |
| 612 | write_mmcr_word(SC520_PIOCLR31_16, 0x0003); |
| 613 | write_mmcr_word(SC520_PIOSET31_16, 0x000c); |
| 614 | break; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 615 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 616 | default: |
| 617 | printf("Illegal SSI device requested: %d\n", dev); |
| 618 | } |
| 619 | } else { |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 620 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 621 | /* Globox board: Both EEPROM and TEMP are active-high */ |
| 622 | |
| 623 | switch (dev) { |
| 624 | case 1: /* EEPROM */ |
| 625 | write_mmcr_word(SC520_PIOSET15_0, 0x0100); |
| 626 | break; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 627 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 628 | case 2: /* Temp Probe */ |
| 629 | write_mmcr_word(SC520_PIOSET15_0, 0x0080); |
| 630 | break; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 631 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 632 | case 0: |
| 633 | write_mmcr_word(SC520_PIOCLR15_0, 0x0180); |
| 634 | break; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 635 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 636 | default: |
| 637 | printf("Illegal SSI device requested: %d\n", dev); |
| 638 | } |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 639 | } |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 640 | } |
| 641 | |
Graeme Russ | 91ee4e1 | 2009-08-23 12:59:54 +1000 | [diff] [blame] | 642 | void spi_eeprom_probe(int x) |
| 643 | { |
| 644 | } |
| 645 | |
| 646 | int spi_eeprom_read(int x, int offset, uchar *buffer, int len) |
| 647 | { |
| 648 | return 0; |
| 649 | } |
| 650 | |
| 651 | int spi_eeprom_write(int x, int offset, uchar *buffer, int len) |
| 652 | { |
| 653 | return 0; |
| 654 | } |
| 655 | |
| 656 | void mw_eeprom_probe(int x) |
| 657 | { |
| 658 | } |
| 659 | |
| 660 | int mw_eeprom_read(int x, int offset, uchar *buffer, int len) |
| 661 | { |
| 662 | return 0; |
| 663 | } |
| 664 | |
| 665 | int mw_eeprom_write(int x, int offset, uchar *buffer, int len) |
| 666 | { |
| 667 | return 0; |
| 668 | } |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 669 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 670 | void spi_init_f(void) |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 671 | { |
| 672 | read_mmcr_byte(SC520_SYSINFO) ? |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 673 | spi_eeprom_probe(1) : |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 674 | mw_eeprom_probe(1); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 675 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 676 | } |
| 677 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 678 | ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len) |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 679 | { |
| 680 | int offset; |
| 681 | int i; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 682 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 683 | offset = 0; |
| 684 | for (i=0;i<alen;i++) { |
| 685 | offset <<= 8; |
| 686 | offset |= addr[i]; |
| 687 | } |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 688 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 689 | return read_mmcr_byte(SC520_SYSINFO) ? |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 690 | spi_eeprom_read(1, offset, buffer, len) : |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 691 | mw_eeprom_read(1, offset, buffer, len); |
| 692 | } |
| 693 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 694 | ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len) |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 695 | { |
| 696 | int offset; |
| 697 | int i; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 698 | |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 699 | offset = 0; |
| 700 | for (i=0;i<alen;i++) { |
| 701 | offset <<= 8; |
| 702 | offset |= addr[i]; |
| 703 | } |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 704 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 705 | return read_mmcr_byte(SC520_SYSINFO) ? |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 706 | spi_eeprom_write(1, offset, buffer, len) : |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 707 | mw_eeprom_write(1, offset, buffer, len); |
| 708 | } |
Ben Warren | 10efa02 | 2008-08-31 20:37:00 -0700 | [diff] [blame] | 709 | |
| 710 | int board_eth_init(bd_t *bis) |
| 711 | { |
| 712 | return pci_eth_init(bis); |
| 713 | } |