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gerrit.cesnet.cz / github / trini / u-boot / bd2313078114c4b44c4a5ce149af43bcb7fc8854 / . / board / renesas / rsk7203 / lowlevel_init.S
blob: 7b9ecd89c318d1821c47b3862054e3e1921210b5 [file] [log] [blame]
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]1/*
2 * Copyright (C) 2008 Nobuhiro Iwamatsu
3 * Copyright (C) 2008 Renesas Solutions Corp.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20#include <config.h>
21#include <version.h>
22
23#include <asm/processor.h>
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]24#include <asm/macro.h>
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]25
26 .global lowlevel_init
27
28 .text
29 .align 2
30
31lowlevel_init:
32 /* Cache setting */
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]33 write32 CCR1_A ,CCR1_D
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]34
35 /* ConfigurePortPins */
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]36 write16 PECRL3_A, PECRL3_D
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]37
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]38 write16 PCCRL4_A, PCCRL4_D0
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]39
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]40 write16 PECRL4_A, PECRL4_D0
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]41
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]42 write16 PEIORL_A, PEIORL_D0
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]43
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]44 write16 PCIORL_A, PCIORL_D
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]45
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]46 write16 PFCRH2_A, PFCRH2_D
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]47
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]48 write16 PFCRH3_A, PFCRH3_D
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]49
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]50 write16 PFCRH1_A, PFCRH1_D
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]51
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]52 write16 PFIORH_A, PFIORH_D
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]53
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]54 write16 PECRL1_A, PECRL1_D0
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]55
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]56 write16 PEIORL_A, PEIORL_D1
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]57
58 /* Configure Operating Frequency */
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]59 write16 WTCSR_A, WTCSR_D0
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]60
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]61 write16 WTCSR_A, WTCSR_D1
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]62
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]63 write16 WTCNT_A, WTCNT_D
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]64
65 /* Set clock mode*/
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]66 write16 FRQCR_A, FRQCR_D
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]67
68 /* Configure Bus And Memory */
69init_bsc_cs0:
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]70 write16 PCCRL4_A, PCCRL4_D1
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]71
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]72 write16 PECRL1_A, PECRL1_D1
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]73
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]74 write32 CMNCR_A, CMNCR_D
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]75
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]76 write32 SC0BCR_A, SC0BCR_D
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]77
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]78 write32 CS0WCR_A, CS0WCR_D
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]79
80init_bsc_cs1:
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]81 write16 PECRL4_A, PECRL4_D1
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]82
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]83 write32 CS1WCR_A, CS1WCR_D
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]84
85init_sdram:
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]86 write16 PCCRL2_A, PCCRL2_D
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]87
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]88 write16 PCCRL4_A, PCCRL4_D2
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]89
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]90 write16 PCCRL1_A, PCCRL1_D
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]91
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]92 write16 PCCRL3_A, PCCRL3_D
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]93
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]94 write32 CS3BCR_A, CS3BCR_D
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]95
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]96 write32 CS3WCR_A, CS3WCR_D
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]97
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]98 write32 SDCR_A, SDCR_D
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]99
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]100 write32 RTCOR_A, RTCOR_D
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]101
Jean-Christophe PLAGNIOL-VILLARDf7e78f32008-12-20 19:29:49 +0100[diff] [blame]102 write32 RTCSR_A, RTCSR_D
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]103
104 /* wait 200us */
Jean-Christophe PLAGNIOL-VILLARDe4430772008-12-20 19:29:48 +0100[diff] [blame]105 mov.l REPEAT_D, r3
106 mov #0, r2
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]107repeat0:
Jean-Christophe PLAGNIOL-VILLARDe4430772008-12-20 19:29:48 +0100[diff] [blame]108 add #1, r2
109 cmp/hs r3, r2
110 bf repeat0
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]111 nop
112
Jean-Christophe PLAGNIOL-VILLARDe4430772008-12-20 19:29:48 +0100[diff] [blame]113 mov.l SDRAM_MODE, r1
114 mov #0, r0
115 mov.l r0, @r1
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]116
117 nop
118 rts
119
120 .align 4
121
122CCR1_A: .long CCR1
123CCR1_D: .long 0x0000090B
124PCCRL4_A: .long 0xFFFE3910
125PCCRL4_D0: .long 0x00000000
126PECRL4_A: .long 0xFFFE3A10
127PECRL4_D0: .long 0x00000000
128PECRL3_A: .long 0xFFFE3A12
129PECRL3_D: .long 0x00000000
130PEIORL_A: .long 0xFFFE3A06
131PEIORL_D0: .long 0x00001C00
132PEIORL_D1: .long 0x00001C02
133PCIORL_A: .long 0xFFFE3906
134PCIORL_D: .long 0x00004000
135PFCRH2_A: .long 0xFFFE3A8C
136PFCRH2_D: .long 0x00000000
137PFCRH3_A: .long 0xFFFE3A8A
138PFCRH3_D: .long 0x00000000
139PFCRH1_A: .long 0xFFFE3A8E
140PFCRH1_D: .long 0x00000000
141PFIORH_A: .long 0xFFFE3A84
142PFIORH_D: .long 0x00000729
143PECRL1_A: .long 0xFFFE3A16
144PECRL1_D0: .long 0x00000033
145
146
147WTCSR_A: .long 0xFFFE0000
Jean-Christophe PLAGNIOL-VILLARDe4430772008-12-20 19:29:48 +0100[diff] [blame]148WTCSR_D0: .long 0x0000A518
149WTCSR_D1: .long 0x0000A51D
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]150WTCNT_A: .long 0xFFFE0002
151WTCNT_D: .long 0x00005A84
152FRQCR_A: .long 0xFFFE0010
153FRQCR_D: .long 0x00000104
154
155PCCRL4_D1: .long 0x00000010
156PECRL1_D1: .long 0x00000133
157
158CMNCR_A: .long 0xFFFC0000
159CMNCR_D: .long 0x00001810
160SC0BCR_A: .long 0xFFFC0004
161SC0BCR_D: .long 0x10000400
162CS0WCR_A: .long 0xFFFC0028
163CS0WCR_D: .long 0x00000B41
164PECRL4_D1: .long 0x00000100
165CS1WCR_A: .long 0xFFFC002C
166CS1WCR_D: .long 0x00000B01
167PCCRL4_D2: .long 0x00000011
168PCCRL3_A: .long 0xFFFE3912
169PCCRL3_D: .long 0x00000011
170PCCRL2_A: .long 0xFFFE3914
171PCCRL2_D: .long 0x00001111
172PCCRL1_A: .long 0xFFFE3916
173PCCRL1_D: .long 0x00001010
174PDCRL4_A: .long 0xFFFE3990
175PDCRL4_D: .long 0x00000011
176PDCRL3_A: .long 0xFFFE3992
177PDCRL3_D: .long 0x00000011
178PDCRL2_A: .long 0xFFFE3994
179PDCRL2_D: .long 0x00001111
180PDCRL1_A: .long 0xFFFE3996
181PDCRL1_D: .long 0x00001000
182CS3BCR_A: .long 0xFFFC0010
183CS3BCR_D: .long 0x00004400
184CS3WCR_A: .long 0xFFFC0034
185CS3WCR_D: .long 0x00002892
186SDCR_A: .long 0xFFFC004C
187SDCR_D: .long 0x00000809
188RTCOR_A: .long 0xFFFC0058
189RTCOR_D: .long 0xA55A0041
190RTCSR_A: .long 0xFFFC0050
191RTCSR_D: .long 0xa55a0010
192
193STBCR3_A: .long 0xFFFE0408
194STBCR3_D: .long 0x00000000
195STBCR4_A: .long 0xFFFE040C
196STBCR4_D: .long 0x00000008
197STBCR5_A: .long 0xFFFE0410
198STBCR5_D: .long 0x00000000
Jean-Christophe PLAGNIOL-VILLARDe4430772008-12-20 19:29:48 +0100[diff] [blame]199STBCR6_A: .long 0xFFFE0414
Nobuhiro Iwamatsuc655fad2008-08-31 23:02:04 +0900[diff] [blame]200STBCR6_D: .long 0x00000002
201SDRAM_MODE: .long 0xFFFC5040
202REPEAT_D: .long 0x00009C40