blob: 5276ce6ab1a2f967780054860f13d05d096cce91 [file] [log] [blame]
Simon Glass91785f72015-01-27 22:13:39 -07001/*
2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <errno.h>
9#include <asm/io.h>
Bin Mengff1e18a2015-10-11 21:37:42 -070010#include <asm/mrccache.h>
Simon Glass91785f72015-01-27 22:13:39 -070011#include <asm/post.h>
12#include <asm/processor.h>
13#include <asm/fsp/fsp_support.h>
14
Simon Glass8b097912015-07-31 09:31:31 -060015DECLARE_GLOBAL_DATA_PTR;
16
Simon Glass91785f72015-01-27 22:13:39 -070017int print_cpuinfo(void)
18{
19 post_code(POST_CPU_INFO);
20 return default_print_cpuinfo();
21}
22
Simon Glass412400a2015-08-10 07:05:07 -060023int fsp_init_phase_pci(void)
Simon Glass91785f72015-01-27 22:13:39 -070024{
25 u32 status;
26
27 /* call into FspNotify */
28 debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
29 status = fsp_notify(NULL, INIT_PHASE_PCI);
Simon Glass412400a2015-08-10 07:05:07 -060030 if (status)
Simon Glass91785f72015-01-27 22:13:39 -070031 debug("fail, error code %x\n", status);
32 else
33 debug("OK\n");
34
Simon Glass412400a2015-08-10 07:05:07 -060035 return status ? -EPERM : 0;
36}
37
Simon Glass91785f72015-01-27 22:13:39 -070038void board_final_cleanup(void)
39{
40 u32 status;
41
42 /* call into FspNotify */
43 debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
44 status = fsp_notify(NULL, INIT_PHASE_BOOT);
Simon Glassecf674b2015-08-12 19:33:07 -060045 if (status)
Simon Glass91785f72015-01-27 22:13:39 -070046 debug("fail, error code %x\n", status);
47 else
48 debug("OK\n");
49
50 return;
51}
Bin Mengaefaff82015-06-07 11:33:14 +080052
Bin Mengff1e18a2015-10-11 21:37:42 -070053static __maybe_unused void *fsp_prepare_mrc_cache(void)
54{
55 struct mrc_data_container *cache;
56 struct mrc_region entry;
57 int ret;
58
59 ret = mrccache_get_region(NULL, &entry);
60 if (ret)
61 return NULL;
62
63 cache = mrccache_find_current(&entry);
64 if (!cache)
65 return NULL;
66
67 debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
68 cache->data, cache->data_size, cache->checksum);
69
70 return cache->data;
71}
72
Bin Mengaefaff82015-06-07 11:33:14 +080073int x86_fsp_init(void)
74{
Bin Mengff1e18a2015-10-11 21:37:42 -070075 void *nvs;
76
Bin Meng57b10f52015-08-20 06:40:19 -070077 if (!gd->arch.hob_list) {
Bin Mengff1e18a2015-10-11 21:37:42 -070078#ifdef CONFIG_ENABLE_MRC_CACHE
79 nvs = fsp_prepare_mrc_cache();
80#else
81 nvs = NULL;
82#endif
Bin Meng57b10f52015-08-20 06:40:19 -070083 /*
84 * The first time we enter here, call fsp_init().
85 * Note the execution does not return to this function,
86 * instead it jumps to fsp_continue().
87 */
Bin Mengff1e18a2015-10-11 21:37:42 -070088 fsp_init(CONFIG_FSP_TEMP_RAM_ADDR, BOOT_FULL_CONFIG, nvs);
Bin Meng57b10f52015-08-20 06:40:19 -070089 } else {
90 /*
91 * The second time we enter here, adjust the size of malloc()
92 * pool before relocation. Given gd->malloc_base was adjusted
93 * after the call to board_init_f_mem() in arch/x86/cpu/start.S,
94 * we should fix up gd->malloc_limit here.
95 */
96 gd->malloc_limit += CONFIG_FSP_SYS_MALLOC_F_LEN;
97 }
Bin Mengaefaff82015-06-07 11:33:14 +080098
99 return 0;
100}